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DAC '98 Proceedings of the 35th annual Design Automation Conference
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Proceedings of the 36th annual ACM/IEEE Design Automation Conference
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Proceedings of the 2002 international symposium on Low power electronics and design
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ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
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VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Defect Simulation Methodology for iDDT Testing
Journal of Electronic Testing: Theory and Applications
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Quick supply current waveform estimation at gate level using existed cell library information
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A SCORE macromodel for PLL designs to analyze supply noise interaction issues at behavioral level
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Fast and accurate analysis of supply noise effects in PLL with noise interactions
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Efficient algorithms for multilevel power estimation of VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logic-Level fast current simulation for digital CMOS circuits
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
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In this paper, we present a new gate-level approach to power and current simulation. We propose a symbolic model of complementary metal-oxide-semiconductor (CMOS) gates to capture the dependence of power consumption and current flows on input patterns and fan-in/fan-out conditions. Library elements are characterized and their models are used during event-driven logic simulation to provide power information and construct time-domain current waveforms. We provide both global and local pattern-dependent estimates of power consumption and current peaks (with accuracy of 6 and 10% from SPICE, respectively), while keeping performance comparable with traditional gate-level simulation with unit delay. We use VERILOG-XL as simulation engine to grant compatibility with design tools based on Verilog HDL. A Web-based user interface allows our simulator (PPP) to be accessed through the Internet using a standard web browser.