Parametric timing and power macromodels for high level simulation of low-swing interconnects

Authors:
Davide Bertozzi;Luca Benini;Bruno Ricco'
Affiliations:
University of Bologna, Bologna Italy;University of Bologna, Bologna Italy;University of Bologna, Bologna Italy
Venue:
Proceedings of the 2002 international symposium on Low power electronics and design
Year:
2002

Citing 9
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Abstract

The impact of global on-chip interconnections on power consumption and speed of integrated circuits is becoming a serious concern. Designers need therefore to quickly estimate how performance and power are affected by a given choice of the interconnection parameters (length, voltage swing, driver and receiver schematics and sizing). This work focuses on the entire communication channel (driver, interconnect, receiver), and provides high level parametric VHDL simulation models for low-swing signaling schemes. These SPICE-derived power and timing macromodels transfer electrical-level information to the RTL simulation in an event-driven fashion, as transitions occur at the input of the interconnect driver. The accuracy reached by this back-annotation technique is within 5% with respect to SPICE results, with only 4% simulation speed penalty in the worst case.