Parametric timing and power macromodels for high level simulation of low-swing interconnects
Proceedings of the 2002 international symposium on Low power electronics and design
Multiobjective Design of Embedded Processors on FPGA Platforms
ICDCSW '04 Proceedings of the 24th International Conference on Distributed Computing Systems Workshops - W7: EC (ICDCSW'04) - Volume 7
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In this paper, we present experimental results obtained during the modeling, design, and implementation of a full set of versions of SPARC v.8 Integer Unit cores aimed at embedded applications. VHDL is the description language, Synopsys is the tool used for logical synthesis, and Duet Technologies' Epoch for obtaining the physical layout of the final circuits. These are mapped to 0.50- and 0.35-/spl mu/m, three metal layer processes in order to study the impact of VLSI scaling on SPARC microarchitectural features. The quantitative results obtained characterize suitable points in the design space. They show the extent to which microarchitecture, design, datapath granularity, and megacell decisions affect performance and cost functions. Design space exploration down to physical layouts is made possible by modeling techniques based on configurable VHDL descriptions.