Flexible design of SPARC cores: a quantitative study
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
FPGA prototyping of a RISC processor core for embedded applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Quantitative study of the impact of design and synthesis options on processor core performance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Rapid-Prototyping Of High-Performance RISC Cores with VHDL
VIUF '97 Proceedings of the 1997 VHDL International User's Forum (VIUF '97)
Synthesis Experiments and Performance Metrics for Evaluating the Quality of IP Blocks and Megacells
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Early Cost/Performance Cache Analysis of a Split MCM-Based MicroSparc CPU
MCMC '96 Proceedings of the 1996 IEEE Multi-Chip Module Conference (MCMC '96)
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
System-Level Design Methodology with Direct Execution For Multiprocessors on SoPC
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
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The design of an embedded microprocessor for a givenworkload is a tremendous task by itself due to the numerousparameters involved and the ranges of their possible values. Ifpower consumption and area are also to be considered then theproblem is even more complicated and requires a suitableframework and methodology for exploring the vastmultidimensional space for such a problem. In this paper wepropose such a framework based on direct execution.