High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Specification and design of embedded systems
Specification and design of embedded systems
Setting up a retrieval system for design reuse—experiences and acceptance
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Complexity-effective superscalar processors
Proceedings of the 24th annual international symposium on Computer architecture
DAC '97 Proceedings of the 34th annual Design Automation Conference
Reuse methodology manual: for system-on-a-chip designs
Reuse methodology manual: for system-on-a-chip designs
Fast prototyping: a system design flow for fast design, prototyping and efficient IP reuse
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Aspects of system-level design
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
MOCSYN: multiobjective core-based single-chip system synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Virtual components application and customization
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Design methodology for IP providers
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A systematic analysis of reuse strategies for design of electronic circuits
Proceedings of the conference on Design, automation and test in Europe
Introducing Core-Based System Design
IEEE Design & Test
Multiobjective Design of Embedded Processors on FPGA Platforms
ICDCSW '04 Proceedings of the 24th International Conference on Distributed Computing Systems Workshops - W7: EC (ICDCSW'04) - Volume 7
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A complete quantitative evaluation of the quality of more than one hundred implementations of SPARC processor core and its related circuitry, synthesized from VHDL descriptions, is presented in this paper as a demonstration example for selecting benchmark circuits, synthesis experiments with different tools and technologies, and performance metrics, for evaluating the quality of IP blocks and megacells. The methodology of the experiments conducted for these circuits can be applied to a wide range of other benchmark candidate circuits. The synthesis experiments are designed to fully explore the synthesis space and to analyze the impact of every synthesis step on the final design quality obtained.