Chip-level modeling with VHDL
Increasing design quality and engineering productivity through design reuse
DAC '93 Proceedings of the 30th international Design Automation Conference
A reuse scenario for the VHDL-based hardware design flow
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
VHDL development system and coding standard
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Basic concepts for an HDL reverse engineering tool-set
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
An efficient reuse system for digital circuit design
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Hardware reuse at the behavioral level
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A systematic analysis of reuse strategies for design of electronic circuits
Proceedings of the conference on Design, automation and test in Europe
Synthesis Experiments and Performance Metrics for Evaluating the Quality of IP Blocks and Megacells
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
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