VHDL synthesis using structured modeling
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Behavioral modeling of transmission gates in VHDL
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Designer controlled behavioral synthesis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
OOPSLA '91 Conference proceedings on Object-oriented programming systems, languages, and applications
ACM SIGDA Newsletter
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Behavioral fault simulation in VHDL
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Register/ file/ cache microarchitecture study using VHDL
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
A system for fault diagnosis and simulation of VHDL descriptions
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
The automatic generation of bus-interface models
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Temporal verification of behavioral descriptions in VHDL
EURO-DAC '92 Proceedings of the conference on European design automation
An evaluation system for distributed-time VHDL simulation
PADS '94 Proceedings of the eighth workshop on Parallel and distributed simulation
Generating VHDL models from natural language descriptions
EURO-DAC '94 Proceedings of the conference on European design automation
EURO-DAC '94 Proceedings of the conference on European design automation
Basic concepts for an HDL reverse engineering tool-set
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Micro-operation perturbations in chip level fault modeling
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Timing distribution in VHDL behavioral models
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
High-Level Embedded System Specifications Based on Process Activation Conditions
Journal of VLSI Signal Processing Systems - Special issue on system level design
Logic Control and “Reactive” Systems: Algorithmization and Programming
Automation and Remote Control
A prototype of a VHDL-based fault injection tool: description and application
Journal of Systems Architecture: the EUROMICRO Journal - Defect and fault tolerance in VLSI Systems
Transparent Logic Modeling in VHDL
IEEE Design & Test
A VHDL Fault Diagnosis Tool Using Functional Fault Models
IEEE Design & Test
Fault Injection into VHDL Models: Experimental Validation of a Fault Tolerant Microcomputer System
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Formal boolean manipulations for the verification of sequential machines
EURO-DAC '90 Proceedings of the conference on European design automation
ACM SIGDA Newsletter
ACM-SE 38 Proceedings of the 38th annual on Southeast regional conference
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