Chip-level modeling with VHDL
Fault Injection for Dependability Validation: A Methodology and Some Applications
IEEE Transactions on Software Engineering
FINE: A Fault Injection and Monitoring Environment for Tracing the UNIX System Behavior Under Faults
IEEE Transactions on Software Engineering - Special issue on software reliability
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Computer
Fault Injection Techniques and Tools
Computer
A Fault Injection Technique for VHDL Behavioral-Level Models
IEEE Design & Test
FOCUS: An Experimental Environment for Fault Sensitivity Analysis
IEEE Transactions on Computers
Fault Injection and Dependability Evaluation of Fault-Tolerant Systems
IEEE Transactions on Computers
MAFALDA: Microkernel Assessment by Fault Injection and Design Aid
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
Assessing Error Detection Coverage by Simulated Fault Injection
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
Fault Injection into VHDL Models: Experimental Validation of a Fault Tolerant Microcomputer System
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
Experimental Validation of High-Speed Fault-Tolerant Systems Using Physical Fault Injection
DCCA '99 Proceedings of the conference on Dependable Computing for Critical Applications
A Comparison of Simulation Based and Scan Chain Implemented Fault Injection
FTCS '98 Proceedings of the The Twenty-Eighth Annual International Symposium on Fault-Tolerant Computing
Design and Validation of a Distributed Industrial Control System's Nodes
SRDS '99 Proceedings of the 18th IEEE Symposium on Reliable Distributed Systems
A prototype of a VHDL-based fault injection tool: description and application
Journal of Systems Architecture: the EUROMICRO Journal - Defect and fault tolerance in VLSI Systems
Enhancement of fault injection techniques based on the modification of VHDL code
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Investigation of transient fault effects in synchronous and asynchronous Network on Chip router
Journal of Systems Architecture: the EUROMICRO Journal
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This work presents a campaign of fault injection to validate the Dependability of a fault tolerant microcomputer system. The system is duplex with cold stand-by sparing, parity detection and a watchdog timer. The faults have been injected on a chip-level VHDL model, using an injection tool designed for this purpose. We have carried out a set of injection experiments (with 3000 injections each), injecting transient faults of types stuck-at, bit-flip, indetermination and delay on both the signals and variables of the system, running two different workloads. We have analyzed the pathology of the propagated errors, measured their latency, and calculated both detection and recovery coverage. For instance, system detection cover-ages (including non-effective errors) up to 98%, and sys-tem recovery coverage up to 94% have been obtained for short transient faults.