A prototype of a VHDL-based fault injection tool: description and application
Journal of Systems Architecture: the EUROMICRO Journal - Defect and fault tolerance in VLSI Systems
Fault Injection into VHDL Models: Experimental Validation of a Fault Tolerant Microcomputer System
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
Design and Validation of a Distributed Industrial Control System's Nodes
SRDS '99 Proceedings of the 18th IEEE Symposium on Reliable Distributed Systems
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Comparison of Physical and Software-Implemented Fault Injection Techniques
IEEE Transactions on Computers
Experiences during the Experimental Validation of the Time-Triggered Architecture
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Evaluating coverage of error detection logic for soft errors using formal methods
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Using NEXUS compliant debuggers for real time fault injection on microprocessors
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Dependability assessment of by-wire control systems using fault injection
Journal of Systems Architecture: the EUROMICRO Journal
Real-time fault injection using enhanced on-chip debug infrastructures
Microprocessors & Microsystems
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This paper introduces a new methodology for validation of dependable systems based on physical fault injection. The approach defines the elements of the injection environment and the requirements that are necessary to control the injection process with fine granularity, allowing for the elimination of glitches and not valid experiments and therefore making the validation process more accurate. We also show the main features of a high-speed pin level fault injection tool, AFIT (Advanced Fault Injection Tool), that incorporates most of the requirements necessary for the application of this methodology. As a practical case study we have validated FASST, a fault tolerant multiprocessor system composed of several fail-silent processor modules. The dependability of the system has been shown, including the influence of the error detection levels in the coverage and latency of the error.