Comparison and Application of Different VHDL-Based Fault Injection Techniques
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Experimental Evaluation of a COTS System for Space Application
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Experimental Validation of High-Speed Fault-Tolerant Systems Using Physical Fault Injection
DCCA '99 Proceedings of the conference on Dependable Computing for Critical Applications
A Technique for Automated Validation of Fault Tolerant Designs Using Laser Fault Injection (LFI)
FTCS '98 Proceedings of the The Twenty-Eighth Annual International Symposium on Fault-Tolerant Computing
Comparison of Physical and Software-Implemented Fault Injection Techniques
IEEE Transactions on Computers
Basic Concepts and Taxonomy of Dependable and Secure Computing
IEEE Transactions on Dependable and Secure Computing
How to Characterize the Problem of SEU in Processors and Representative Errors Observed on Flight
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
A Modified Debugging Infrastructure to Assist Real Time Fault Injection Campaigns
DDECS '06 Proceedings of the 2006 IEEE Design and Diagnostics of Electronic Circuits and systems
A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures
Proceedings of the 21st annual symposium on Integrated circuits and system design
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As electronic devices get smaller and more complex, dependability assurance is becoming fundamental for many mission critical computer based systems. This paper presents a case study on the possibility of using the on-chip debug infrastructures present in most current microprocessors to execute real time fault injection campaigns. The proposed methodology is based on a debugger customized for fault injection and designed for maximum flexibility, and consists of injecting bit-flip type faults on memory elements without modifying or halting the target application. The debugger design is easily portable and applicable to different architectures, providing a flexible and efficient mechanism for verifying and validating fault tolerant components.