Validating fault tolerant designs using laser fault injection (LFI)
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
Experimental Validation of High-Speed Fault-Tolerant Systems Using Physical Fault Injection
DCCA '99 Proceedings of the conference on Dependable Computing for Critical Applications
A Comparison of Simulation Based and Scan Chain Implemented Fault Injection
FTCS '98 Proceedings of the The Twenty-Eighth Annual International Symposium on Fault-Tolerant Computing
On-line Error Detection Techniques for Dependable Embedded Processors with High Complexity
IOLTW '01 Proceedings of the Seventh International On-Line Testing Workshop
Event-Centric Simulation of Crosstalk Pulse Faults in Sequential Circuits
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Automatic Formal Verification of Fused-Multiply-Add FPUs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Soft Errors in Advanced Computer Systems
IEEE Design & Test
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
On-line error detection and fast recover techniques for dependable embedded processors
On-line error detection and fast recover techniques for dependable embedded processors
Efficient symbolic simulation via dynamic scheduling, don't caring, and case splitting
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Verification-guided soft error resilience
Proceedings of the conference on Design, automation and test in Europe
Integration, the VLSI Journal
Computing bounds for fault tolerance using formal techniques
Proceedings of the 46th Annual Design Automation Conference
ACL2 for the verification of fault-tolerance properties: first results
Proceedings of the Eighth International Workshop on the ACL2 Theorem Prover and its Applications
Verification for fault tolerance of the IBM system z microprocessor
Proceedings of the 47th Design Automation Conference
Towards robustness analysis using PVS
ITP'11 Proceedings of the Second international conference on Interactive theorem proving
Feasibility analysis for robustness quantification by symbolic model checking
Formal Methods in System Design
Assessing system vulnerability using formal verification techniques
MEMICS'11 Proceedings of the 7th international conference on Mathematical and Engineering Methods in Computer Science
Hardware dependability in the presence of soft errors
VoCS'08 Proceedings of the 2008 international conference on Visions of Computer Science: BCS International Academic Conference
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In this paper we describe a methodology to measure exactly the quality of fault-tolerant designs by combining fault-injection in high level design (HLD) descriptions with a formal verification approach. We utilize BDD based symbolic simulation to determine the coverage of online error-detection and - correction logic. We describe an easily portable approach, which can be applied to a wide variety of multi-GHz industrial designs.