On-line Error Detection Techniques for Dependable Embedded Processors with High Complexity

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Venue:
IOLTW '01 Proceedings of the Seventh International On-Line Testing Workshop
Year:
2001

Citing 0
Cited 4

Online Check and Recovery Techniques for Dependable Embedded Processors

IEEE Micro
On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check

Journal of Electronic Testing: Theory and Applications
Evaluating coverage of error detection logic for soft errors using formal methods

Proceedings of the conference on Design, automation and test in Europe: Proceedings
On-line error detection and fast recover techniques for dependable embedded processors

On-line error detection and fast recover techniques for dependable embedded processors

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Abstract

Abstract: This paper presents efficient techniques for concurrent error detection of processor components. It deals with concurrent check methods for complex data-path elements like FPUs or register-files. We propose a Berger code prediction unit for a multistage add-sub-FPU. Furthermore, the suitability of Berger code for register-files is discussed. As an alternative, the Cross-Parity observation is introduced. The applicability of these concepts was evaluated on several experimental processor designs up to double-precision pipeline processors.