Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Formal hardware verification by symbolic ternary trajectory evaluation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Symbolic model checking: an approach to the state explosion problem
Symbolic model checking: an approach to the state explosion problem
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
Symbolic Model Checking
Rapid Prototyping of Digital Systems: A Tutorial Approach
Rapid Prototyping of Digital Systems: A Tutorial Approach
Computer
Fault Injection Techniques and Tools
Computer
Opportunistic Transient-Fault Detection
Proceedings of the 32nd annual international symposium on Computer Architecture
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
The effects of energy management on reliability in real-time embedded systems
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Evaluating coverage of error detection logic for soft errors using formal methods
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Symmetry Reduction for STE Model Checking
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
A New Approach for Transient Fault Injection Using Symbolic Simulation
IOLTS '08 Proceedings of the 2008 14th IEEE International On-Line Testing Symposium
Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
An industrially effective environment for formal hardware verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A simple theorem prover based on symbolic trajectory evaluation and BDD's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Using formal verification for designing hardware designs free from logic design bugs has been an active area of research since the last 15 years. Technology has matured and we have a choice of formal tools such as model checkers, equivalence checkers, and a range of theorem provers. Hardware reliability and fault tolerance has been studied for a long time as well, and some good solutions in the form of redundancy are available for making hardware resilient against faults. However, understanding the impact of a particular kind of fault known as a single-event-upset (SEU) or a transient fault especially in the context of low-power design is not well understood, and therefore achieving adequate tolerance for low-power processors against SEUs is still very much an open problem. A significant bottleneck in this has been the traditional fault injection methodology whereby the impact of a fault is analysed whilst a processor is running a specific binary program image. Thus the true impact of the fault is limited by the shadow of the particular program. Another key problem has been the modification of the original design to incorporate fault injection hardware. Thus, the design being checked for faults is different from the original design. In this paper we report on our experiences on studying transient fault injection on a 32 bit multi-cycle RISC processor using the formal specification and verification framework of Symbolic Trajectory Evaluation (STE). Our approach offers the benefit of studying fault injection by not modifying the original design and doing it in a program independent way. The vulnerability of the processor is assessed in terms of its architecural features, which is possible due to symbolic model checking.