The formal verification of a pipelined double-precision IEEE floating-point multiplier
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Generalized Symbolic Trajectory Evaluation - Abstraction in Action
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
A Light-Weight Framework for Hardware Verification
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Lifted-FL: A Pragmatic Implementation of Combined Model Checking and Theorem Proving
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
Divider Circuit Verification with Model Checking and Theorem Proving
TPHOLs '00 Proceedings of the 13th International Conference on Theorem Proving in Higher Order Logics
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Introduction to generalized symbolic trajectory evaluation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Enhanced symbolic simulation for efficient verification of embedded array systems
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A Survey of Hybrid Techniques for Functional Verification
IEEE Design & Test
Selective state retention design using symbolic simulation
Proceedings of the Conference on Design, Automation and Test in Europe
Exploring structural symmetry automatically in symbolic trajectory evaluation
Formal Methods in System Design
An integrated approach to verifying large circuits: a case study
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
Hardware dependability in the presence of soft errors
VoCS'08 Proceedings of the 2008 international conference on Visions of Computer Science: BCS International Academic Conference
| Hi-index | 0.03 |
Formal hardware verification based on symbolic trajectory evaluation shows considerable promise in verifying medium to large scale VLSI designs with a high degree of automation. However, in order to verify today's designs, a method for composing partial verification results is needed. This paper presents a theory of composition for symbolic trajectory evaluation and shows how implementing this theory using a specialized theorem prover is very attractive. Symbolic trajectory evaluation is used to prove low level properties of a circuit, and these properties are combined using the prover. Providing a powerful and flexible interface to a coherent system (with automatic assistance in parts) reduces the load on the human verifier. This hybrid approach, coupled with powerful and simple data representation, increases the range of circuits which can be verified using trajectory evaluation. The paper concludes with two examples. One example is the complete verification of a 64 b multiplier which takes approximately 15 minutes on a SPARC 10 machine