Formal Methods Applied to a Floating-Point Number System
IEEE Transactions on Software Engineering
A proof of the nonrestoring division algorithm and its implementation on an ALU
Formal Methods in System Design - Special issue on designing correct circuits
Non-Restoring Integer Square Root: A Case Study in Design by Principled Optimization
TPCD '94 Proceedings of the Second International Conference on Theorem Provers in Circuit Design - Theory, Practice and Experience
Verification of Arithmetic Functions with Binary Moment Diagrams
Verification of Arithmetic Functions with Binary Moment Diagrams
VOSS - A Formal Hardware Verification System User''s Guide
VOSS - A Formal Hardware Verification System User''s Guide
A simple theorem prover based on symbolic trajectory evaluation and BDD's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combining theorem proving and trajectory evaluation in an industrial environment
DAC '98 Proceedings of the 35th annual Design Automation Conference
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Light-Weight Framework for Hardware Verification
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Lifted-FL: A Pragmatic Implementation of Combined Model Checking and Theorem Proving
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
Formal Verification of the VAMP Floating Point Unit
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Formalization of Cadence SPW Fixed-Point Arithmetic in HOL
IFM '02 Proceedings of the Third International Conference on Integrated Formal Methods
Automatic Formal Verification of Fused-Multiply-Add FPUs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Exploiting PSL standard assertions in a theorem-proving-based verification environment
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Formal Verification of the VAMP Floating Point Unit
Formal Methods in System Design
Enhanced symbolic simulation for efficient verification of embedded array systems
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Formalization of fixed-point arithmetic in HOL
Formal Methods in System Design
A Survey of Hybrid Techniques for Functional Verification
IEEE Design & Test
Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Challenges for formal verification in industrial setting
FMICS'06/PDMC'06 Proceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology
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Floating-point circuits are notoriously difficult to design and verify. For verification, simulation barely offers adequate coverage, conventional model-checking techniques are infeasible, and theorem-proving based verification is not sufficiently mature. In this paper we present the formal verification of a radix-eight, pipelined, IEEE double-precision floating-point multiplier. The verification was carried out using a mixture of model-checking and theorem-proving techniques in the Voss hardware verification system. By combining model-checking and theorem-proving we were able to build on the strengths of both areas and achieve significant results with a reasonable amount of effort.