Formal Methods Applied to a Floating-Point Number System
IEEE Transactions on Software Engineering
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IEEE Transactions on Computers
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ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
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FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
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CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
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This paper addresses the formalization in higher-order logic of fixed-point arithmetic based on the SPW (Signal Processing WorkSystem) tool. We encoded the fixed-point number system and specified the different rounding modes in fixed-point arithmetic such as the directed and even rounding modes.We also considered the formalization of exceptions detection and their handling like overflow and invalid operation. An error analysis is then performed to check the correctness of the rounding and to verify the basic arithmetic operations, addition, subtraction, multiplication and division against their mathematical counterparts. Finally, we showed by an example how this formalization can be used to enable the verification of the transition from the floating-point to fixed-point algorithmic levels in the design flow of signal processors.