A proof of the nonrestoring division algorithm and its implementation on an ALU
Formal Methods in System Design - Special issue on designing correct circuits
The formal verification of a pipelined double-precision IEEE floating-point multiplier
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
A Mechanically Checked Proof of the AMD5K86TM Floating-Point Division Program
IEEE Transactions on Computers
Computer Architecture: Complexity and Correctness
Computer Architecture: Complexity and Correctness
A Mechanically Checked Proof of Correctness of the AMD K5 Floating Point Square Root Microcode
Formal Methods in System Design
Verification of IEEE Compliant Subtractive Division Algorithms
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
A Machine-Checked Theory of Floating Point Arithmetic
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
Formal Verification of the VAMP Floating Point Unit
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Verification of Floating-Point Adders
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Modular Verification of SRT Division
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Verifying the SRT Division Algorithm Using Theorem Proving Techniques
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
PVS: A Prototype Verification System
CADE-11 Proceedings of the 11th International Conference on Automated Deduction: Automated Deduction
On the Design of IEEE Compliant Floating Point Units
ARITH '97 Proceedings of the 13th Symposium on Computer Arithmetic (ARITH '97)
Defining the IEEE-854 Floating-Point Standard in PVS
Defining the IEEE-854 Floating-Point Standard in PVS
Formal Verification of the VAMP Floating Point Unit
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Formalization of Cadence SPW Fixed-Point Arithmetic in HOL
IFM '02 Proceedings of the Third International Conference on Integrated Formal Methods
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We report on the formal verification of the floating point unit used in the VAMP processor. The FPU is fully IEEE compliant, and supports denormals and exceptions in hardware. The supported operations are addition, subtraction, multiplication, division, comparison, and conversions. The hardware is verified on the gate level against a formal description of the IEEE standard by means of the theorem prover PVS.