Better verification through symmetry
Formal Methods in System Design - Special issue on symmetry in automatic verification
Formal verification of pipeline control using controlled token nets and abstract interpretation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Model checking
Proceedings of the 37th Annual Design Automation Conference
Formal verification of iterative algorithms in microprocessors
Proceedings of the 37th Annual Design Automation Conference
A methodology for hardware verification using compositional model checking
Science of Computer Programming - Special issue on mathematics of program construction
ACM Transactions on Computational Logic (TOCL)
Reasoning About Pipelines with Structural Hazards
TPCD '94 Proceedings of the Second International Conference on Theorem Provers in Circuit Design - Theory, Practice and Experience
Characterizing Correctness Properties of Parallel Programs Using Fixpoints
Proceedings of the 7th Colloquium on Automata, Languages and Programming
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
A HOL Conversion for Translating Linear Time Temporal Logic to omega-Automata
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
Formal Verification of the VAMP Floating Point Unit
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Processor Verification with Precise Exeptions and Speculative Execution
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Verifying Advanced Microarchitectures that Support Speculation and Exceptions
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
An Integration of Model Checking with Automated Proof Checking
Proceedings of the 7th International Conference on Computer Aided Verification
PVS: A Prototype Verification System
CADE-11 Proceedings of the 11th International Conference on Automated Deduction: Automated Deduction
An efficient algorithm for exploiting multiple arithmetic units
IBM Journal of Research and Development
Modeling and validation of pipeline specifications
ACM Transactions on Embedded Computing Systems (TECS)
Automatic Formal Verification of Fused-Multiply-Add FPUs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Formal Verification of the VAMP Floating Point Unit
Formal Methods in System Design
Functional test generation using property decompositions for validation of pipelined processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Specification-driven directed test generation for validation of pipelined processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Functional test generation using design and property decomposition techniques
ACM Transactions on Embedded Computing Systems (TECS)
A novel verification technique to uncover out-of-order DUV behaviors
Proceedings of the 46th Annual Design Automation Conference
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We describe a methodology for the formal verification of complex out-of-order pipelines as they may be used as execution units in out-of-order processors. The pipelines may process multiple instructions simultaneously, may have branches and cycles in the pipeline structure, may have variable latency, and may reorder instructions internally. The methodology combines model-checking for the verification of the pipeline control, and theorem proving for the verification of the pipeline functionality. In order to combine both techniques, we formally verify that the FairCTL operators defined in 驴-calculus match their intended semantics expressed in a form where computation traces are explicit, since this form is better suited for theorem proving. This allows the formally safe translation of model-checked properties of the pipeline control into a theorem-proving friendly form, which is used for the verification of the overall correctness, including the functionality. As an example we prove the correctness of the pipeline of a multiplication/division floating point unit with all the features mentioned above.