Techniques for verifying superscalar microprocessors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Symbolic Model Checking
The Architecture of Symbolic Computers
The Architecture of Symbolic Computers
Bit-Level Abstraction in the Verfication of Pipelined Microprocessors by Correspondence Checking
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Verifying out-of-order executions
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
Formal Verification of Out-of-Order Execution Using Incremental Flushing
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
BDD Based Procedures for a Theory of Equality with Uninterpreted Functions
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Verification of an Implementation of Tomasulo's Algorithm by Compositional Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Processor Verification with Precise Exeptions and Speculative Execution
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Decomposing the Proof of Correctness of pipelined Microprocessors
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Automatic Datapath Abstraction In Hardware Systems
Proceedings of the 7th International Conference on Computer Aided Verification
The Implementation of Functional Programming Languages (Prentice-Hall International Series in Computer Science)
ACM Transactions on Computational Logic (TOCL)
Formal Verification of Out-of-Order Execution with Incremental Flushing
Formal Methods in System Design
Formal Methods in System Design
Bit-Level Abstraction in the Verfication of Pipelined Microprocessors by Correspondence Checking
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Modeling and Verification of Out-of-Order Microprocessors in UCLID
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
A Comparison of Two Verification Methods for Speculative Instruction Execution
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Verification of Infinite State Systems by Compositional Model Checking
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
A Proof of Correctness of a Processor Implementing Tomasulo's Algorithm without a Reorder Buffer
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
A Framework for Microprocessor Correctness Statements
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Validation of Pipelined Processor Designs Using Esterel Tools: A Case Study
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Exploiting Positive Equality in a Logic of Equality with Uninterpreted Functions
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Formal Verification of a Complex Pipelined Processor
Formal Methods in System Design
Counterexample-guided abstraction refinement for symbolic model checking
Journal of the ACM (JACM)
A general decomposition strategy for verifying register renaming
Proceedings of the 41st annual Design Automation Conference
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Modeling a system controller for timing analysis
EMSOFT '06 Proceedings of the 6th ACM & IEEE International conference on Embedded software
A New Approach for the Construction of Multiway Decision Graphs
Proceedings of the 5th international colloquium on Theoretical Aspects of Computing
NuMDG: a new tool for multiway decision graphs construction
Journal of Computer Science and Technology - Special issue on natural language processing
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We present a new approach to the verification of hardware systems with data dependencies using temporal logic symbolic model checking. As a benchmark we take Tomasulo's algorithm [10] for out-of-order instruction scheduling. Our approach is similar to the idea of uninterpreted function symbols [4].We use symbolic values and instructions instead of concrete ones. This allows us to show the correctness of the machine independently of the actual instruction set architecture and the implementation of the functional units. Instead of using first order terms as in [4], we represent symbolic values with a new compact encoding. In addition, we apply some other reduction techniques to the model. This significantly reduces the state space and allows the use of highly efficient symbolic model checkers like SMV instead of special decision procedures. The correctness of the method has been proven formally with the PVS theorem prover.