Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Better verification through symmetry
Formal Methods in System Design - Special issue on symmetry in automatic verification
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Expressing interesting properties of programs in propositional temporal logic
POPL '86 Proceedings of the 13th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Symbolic Model Checking
The Architecture of Symbolic Computers
The Architecture of Symbolic Computers
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Verifying out-of-order executions
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
Formal Verification of Out-of-Order Execution Using Incremental Flushing
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
BDD Based Procedures for a Theory of Equality with Uninterpreted Functions
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Verification of an Implementation of Tomasulo's Algorithm by Compositional Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Processor Verification with Precise Exeptions and Speculative Execution
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Decomposing the Proof of Correctness of pipelined Microprocessors
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Automatic Datapath Abstraction In Hardware Systems
Proceedings of the 7th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Relating Multi-step and Single-Step Microprocessor Correctness Statements
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Formal Verification of a Complex Pipelined Processor
Formal Methods in System Design
A framework for systematic validation and debugging of pipeline simulators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Testing diagnostics of modern microprocessors with the use of functional models
Automation and Remote Control
Verifiably-safe software-defined networks for CPS
Proceedings of the 2nd ACM international conference on High confidence networked systems
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We present a new technique for verification of complex hardware devices that allows both generality and a high degree of automation. The technique is based on our new way of constructing a “light-weight” completion function together with new encoding of uninterpreted functions called reference file representation.Our technique combines our completion function method and reference file representation with compositional model checking and theorem proving. This extends the state of the art in two directions. First, we obtain a more general verification methodology. Second, it is easier to use, since it has a higher degree of automation.As a benchmark, we take Tomasulo's algorithm for scheduling out-of-order instruction execution used in many modern superscalar processors like the Pentium-II and the PowerPC 604. The algorithm is parameterized by the processor configuration, and our approach allows us to prove its correctness in general, independent of any actual design.