Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Formal Verification for Fault-Tolerant Architectures: Prolegomena to the Design of PVS
IEEE Transactions on Software Engineering
Formal Methods in System Design
Verifying the FM9801 Microarchitecture
IEEE Micro
Formal Verification of a Pipelined Microprocessor
IEEE Software
Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Proceedings of the 8th International Conference on Computer Aided Verification
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Proceedings of the 10th International Conference on Computer Aided Verification
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Proceedings of the 11th International Conference on Computer Aided Verification
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Proceedings of the 12th International Conference on Computer Aided Verification
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Automatic Generation of Invariants in Processor Verification
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Verification of Data-Insensitive CIrcuits: An In-Order-Retirement Case Study
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Reducing Manual Abstraction in Formal Verification of Out-of-Order Execution
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Trace Table Based Approach for Pipeline Microprocessor Verification
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Verification of an Implementation of Tomasulo's Algorithm by Compositional Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Processor Verification with Precise Exeptions and Speculative Execution
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Decomposing the Proof of Correctness of pipelined Microprocessors
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Formal Verification of VLIW Microprocessors with Speculative Execution
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Verifying Advanced Microarchitectures that Support Speculation and Exceptions
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Protocol Verification by Aggregation of Distributed Transactions
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Powerful Techniques for the Automatic Generation of Invariants
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Systematic verification of pipelined microprocessors
Systematic verification of pipelined microprocessors
Formal Verification of Pipelined Microprocessors with Delayed Branches
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
SAEPTUM: verification of ELAN hardware specifications using the proof assistant PVS
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Algebraic models of simultaneous multithreaded and multi-core processors
CALCO'07 Proceedings of the 2nd international conference on Algebra and coalgebra in computer science
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This paper addresses the problem of formally verifying the correctness of a complex pipelined microprocessor at the micro-architectural level of abstraction. The design verified is an example out-of-order execution processor with a reorder buffer, a store buffer, branch prediction, speculative execution and exceptions. We propose a systematic approach called the Completion Functions Approach to decompose and incrementally build its proof of correctness. The central idea is to construct the abstraction function using completion functions, one per unfinished instruction, each of which specifies the effect on the programmer visible state components of completing the instruction. This construction of the abstraction function leads to a very natural decomposition of the proof into proving a series of verification conditions. The approach prescribes a systematic way to generate these verification conditions which can then be discharged with a high degree of automation using techniques based on decision procedures and rewriting. The verification was completed in 34 person days, which we believe, is a modest investment in return for the significant benefits of formal verification.