A structural induction theorem for processes
Information and Computation
Abstract interpretation of reactive systems
ACM Transactions on Programming Languages and Systems (TOPLAS)
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Theory of Program Structures: Schemes, Semantics, Verification
Theory of Program Structures: Schemes, Semantics, Verification
A Tutorial on Using PVS for Hardware Verification
TPCD '94 Proceedings of the Second International Conference on Theorem Provers in Circuit Design - Theory, Practice and Experience
Verification Using Uninterpreted Functions and Finite Instantiations
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
The Need for Formal Methods for Integrated Circuit Design
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Herbrand Automata for Hardware Verification
CONCUR '98 Proceedings of the 9th International Conference on Concurrency Theory
Verifying out-of-order executions
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
Veryfying Parameterized Networks using Abstraction and Regular Languages
CONCUR '95 Proceedings of the 6th International Conference on Concurrency Theory
A Compositional Rule for Hardware Design Refinement
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Formal Verification of Out-of-Order Execution Using Incremental Flushing
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Verification of an Implementation of Tomasulo's Algorithm by Compositional Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Processor Verification with Precise Exeptions and Speculative Execution
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Property Preserving Simulations
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Ground Temporal Logic: A Logic for Hardware Verification
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Model Checking in a Microprocessor Design Project
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Stepwise Refinement of Distributed Systems, Models, Formalisms, Correctness, REX Workshop
Automatic Generation of Invariants and Assertions
CP '95 Proceedings of the First International Conference on Principles and Practice of Constraint Programming
Verifying Tomasulo''s Algorithm by Refinement
Verifying Tomasulo''s Algorithm by Refinement
A Comparison of Two Verification Methods for Speculative Instruction Execution
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
A Framework for Microprocessor Correctness Statements
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
FM-Trends 98 Proceedings of the International Workshop on Current Trends in Applied Formal Method: Applied Formal Methods
Formal Verification of a Complex Pipelined Processor
Formal Methods in System Design
A general decomposition strategy for verifying register renaming
Proceedings of the 41st annual Design Automation Conference
| Hi-index | 0.00 |
There is a large class of circuits (including pipeline and out-of-order execution components) which can be formally verified while completely ignoring the precise characteristics (e.g. word-size) of the data manipulated by the circuits. In the literature, this is often described as the use of uninterpreted functions, implying that the concrete operations applied to the data are abstracted into unknown and featureless functions. In this paper, we briefly introduce an abstract unifying model for such data-insensitive circuits, and claim that the development of such models, perhaps even a theory of circuit schemas, can significantly contribute to the development of efficient and comprehensive verification algorithms combining deductive as well as enumerative methods.As a case study, we present in this paper an algorithm for out-of-order execution with in-order retirement and show it to be a refinement of the sequential instruction execution algorithm. Refinement is established by deductively proving (using pvs) that the register files of the out-of-order algorithm and the sequential algorithm agree at all times if the two systems are synchronized at instruction retirement time.