Herbrand Automata for Hardware Verification

Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic

ACM Transactions on Computational Logic (TOCL)

Verification of Data-Insensitive CIrcuits: An In-Order-Retirement Case Study

FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design

Exploiting Positive Equality in a Logic of Equality with Uninterpreted Functions

CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification

A New Approach for the Construction of Multiway Decision Graphs

Proceedings of the 5th international colloquium on Theoretical Aspects of Computing

NuMDG: a new tool for multiway decision graphs construction

Journal of Computer Science and Technology - Special issue on natural language processing

Automatic formal verification of liveness for pipelined processors with multicycle functional units

CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods