Fast Decision Procedures Based on Congruence Closure
Journal of the ACM (JACM)
Bit-Level Abstraction in the Verfication of Pipelined Microprocessors by Correspondence Checking
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Herbrand Automata for Hardware Verification
CONCUR '98 Proceedings of the 9th International Conference on Concurrency Theory
BDD Based Procedures for a Theory of Equality with Uninterpreted Functions
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Deciding Equality Formulas by Small Domains Instantiations
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Correctness of Pipelined Machines
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Modeling and Verification of Out-of-Order Microprocessors in UCLID
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
On Solving Presburger and Linear Arithmetic with SAT
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Checking Satisfiability of First-Order Formulas by Incremental Translation to SAT
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Finite Instantiations in Equivalence Logic with Uninterpreted Functions
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
ICTAC '09 Proceedings of the 6th International Colloquium on Theoretical Aspects of Computing
NuMDG: a new tool for multiway decision graphs construction
Journal of Computer Science and Technology - Special issue on natural language processing
Yet another decision procedure for equality logic
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Decision procedures customized for formal verification
CADE' 20 Proceedings of the 20th international conference on Automated Deduction
Symbolic bounded conformance checking of model programs
PSI'09 Proceedings of the 7th international Andrei Ershov Memorial conference on Perspectives of Systems Informatics
Unbounded data model verification using SMT solvers
Proceedings of the 27th IEEE/ACM International Conference on Automated Software Engineering
Data model property inference and repair
Proceedings of the 2013 International Symposium on Software Testing and Analysis
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In using the logic of equality with unininterpreted functions to verify hardware systems, specific characteristics of the formula describing the correctness condition can be exploited when deciding its validity.We distinguish a class of terms we call "p-terms" for which equality comparisons can appear only in monotonically positive formulas. By applying suitable abstractions to the hardware model, we can express the functionality of data values and instruction addresses flowing through an instruction pipeline with p-terms. Adecision procedure can exploit the restricted uses of p-terms by considering only "maximally diverse" interpretations of the associated function symbols, where every function application yields a different value except when constrained by functional consistency.We present a procedure that translates the original formula into one in propositional logic by interpreting the formula over a domain of fixedlength bit vectors and using vectors of propositional variables to encode domain variables. By exploiting maximal diversity, this procedure can greatly reduce the number of propositional variables that must be introduced. We present experimental results demonstrating the efficiency of this approach when verifying pipelined processors using the method proposed by Burch and Dill. Exploiting positive equality allows us to overcome the exponential blowup experienced previously [VB98] when verifying microprocessors with load, store, and branch instructions.