Verification of a simple pipelined machine model
Computer-Aided reasoning
Computer-Aided Reasoning: An Approach
Computer-Aided Reasoning: An Approach
Structured Theory Development for a Mechanized Logic
Journal of Automated Reasoning
ACL2 Theorems About Commercial Microprocessors
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
A Proof of Correctness of a Processor Implementing Tomasulo's Algorithm without a Reorder Buffer
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
A Simple Characterization of Stuttering Bisimulation
Proceedings of the 17th Conference on Foundations of Software Technology and Theoretical Computer Science
Trace Table Based Approach for Pipeline Microprocessor Verification
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Verification of an Implementation of Tomasulo's Algorithm by Compositional Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Processor Verification with Precise Exeptions and Speculative Execution
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Decomposing the Proof of Correctness of pipelined Microprocessors
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Deciding Equality Formulas by Small Domains Instantiations
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Linking Theorem Proving and Model-Checking with Well-Founded Bisimulation
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Assume-Guarantee Refinement Between Different Time Scales
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Exploiting Positive Equality in a Logic of Equality with Uninterpreted Functions
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Formal verification of an advanced pipelined machine
Formal verification of an advanced pipelined machine
A Framework for Microprocessor Correctness Statements
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Rewriting for Symbolic Execution of State Machine Models
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Refinement Maps for Efficient Verification of Processor Models
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Verification of executable pipelined machines with bit-level interfaces
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A complete compositional reasoning framework for the efficient verification of pipelined machines
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Automatic verification of safety and liveness for pipelined machines using WEB refinement
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The Challenge of Hardware-Software Co-verification
Verified Software: Theories, Tools, Experiments
Getting Formal Verification into Design Flow
FM '08 Proceedings of the 15th international symposium on Formal Methods
Modelling and verification of superscalar Micro-architectures functional approach
ICCOMP'08 Proceedings of the 12th WSEAS international conference on Computers
A refinement-based compositional reasoning framework for pipelined machine verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimization techniques for verification of out-of-order execution machines
Journal of Electrical and Computer Engineering
CALCO'05 Proceedings of the First international conference on Algebra and Coalgebra in Computer Science
Desynchronization: design for verification
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Refinement and theorem proving
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
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The correctness of pipelined machines is a subject that has been studied extensively. Most of the recent work has used variants of the Burch and Dill notion of correctness [4]. As new features are modeled, e.g., interrupts, new notions of correctness are developed. Given the plethora of correctness conditions, the question arises: what is a reasonable notion of correctness? We discuss the issue at length and show, by mechanical proof, that variants of the Burch and Dill notion of correctness are flawed. We propose a notion of correctness based on WEBs (Well-founded Equivalence Bisimulations) [16,19]. Briefly, our notion of correctness implies that the ISA (Instruction Set Architecture) and MA (Micro-Architecture) machines have the same observable infinite paths, up to stuttering. This implies that the two machines satisfy the same CTL*\X properties and the same safety and liveness properties (up to stuttering).To test the utility of the idea, we use ACL2 to verify several variants of the simple pipelined machine described by Sawada in [22, 23]. Our variants extend the basic machine by adding exceptions (to deal with overflows), interrupts, and fleshed-out 128-bit ALUs (one of which is described in a netlist language). In all cases, we prove the same final theorem. We develop a methodology with mechanical support that we used to verify Sawada's machine. The resulting proof is substantially shorter than the original and does not require any intermediate abstractions; in fact, given the definitions and some general-purpose books (collections of theorems), the proof is automatic. A practical and noteworthy feature of WEBs is their compositionality. This allows us to prove the correctness of the more elaborate machines in manageable stages.