Techniques for verifying superscalar microprocessors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A Practical Methodology for the Formal Verification of RISC Processors
Formal Methods in System Design
Proceedings of the 37th Annual Design Automation Conference
Correctness of Pipelined Machines
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Modeling and Verification of Out-of-Order Microprocessors in UCLID
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Decomposing the Proof of Correctness of pipelined Microprocessors
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
Proceedings of the conference on Design, automation and test in Europe
Algebraic specification and verification of processor microarchitectures
Algebraic specification and verification of processor microarchitectures
CALCO'05 Proceedings of the First international conference on Algebra and Coalgebra in Computer Science
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Most proof approaches verified a pipelined Micro-Architectural (MA) implementation against an Instruction-Set-Architecture (ISA) specification, and consequently, it was impossible to find a meaningful point where the implementation state and the specification state can be compared easily. An alternative solution to such problem is to verify a pipelined micro-architectural implementation against a sequential multi-cycle implementation. Because both models are formalised in terms of clock cycles, all synchronous intermediate states represent interesting points where the comparison could be achieved easily. Furthermore, by decomposing the state, the overall proof decomposes systematically into a set of verification conditions more simple to reason about and to verify. A major advantage of this elegant choice is the ability to carry out the proof by induction within the same specification language rather than by symbolic simulation through a proof tool which remains very tedious. Also, because both models relate to the MA level, there is no need for a data abstraction function, only a time abstraction function is needed to map between the times used by the two models. The potential features of the proposed proof methodology are demonstrated over the pipelined and the superscalar pipelined MIPS processors within Haskell framework.