Automatic test program generation for pipelined processors
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Formal Verification for Fault-Tolerant Architectures: Prolegomena to the Design of PVS
IEEE Transactions on Software Engineering
Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Efficient validity checking for processor verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Techniques for verifying superscalar microprocessors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A scalable formal verification methodology for pipelined microprocessors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Verifying correct pipeline implementation for microprocessors
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A decision procedure for bit-vector arithmetic
DAC '98 Proceedings of the 35th annual Design Automation Conference
Formal verification of pipeline control using controlled token nets and abstract interpretation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A Practical Methodology for the Formal Verification of RISC Processors
Formal Methods in System Design
Automatic verification of scheduling results in high-level synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
High-level test generation for design verification of pipelined microprocessors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
DIVA: a reliable substrate for deep submicron microarchitecture design
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Proceedings of the 37th Annual Design Automation Conference
Formal specification and verification of a dataflow processor array
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A Buffer-Oriented Methodology for Microarchitecture Validation
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
An RTL Abstraction Technique for Processor MicroarchitectureValidation and Test Generation
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
ACM Transactions on Computational Logic (TOCL)
Automated Correctness Condition Generation for Formal Verification ofSynthesized RTL Designs
Formal Methods in System Design - Special issue on formal methods for computer-added design
Scalable hybrid verification of complex microprocessors
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 38th annual Design Automation Conference
Nuts and bolts of core and SoC verification
Proceedings of the 38th annual Design Automation Conference
Achieving maximum performance: a method for the verification of interlocked pipeline control logic
Proceedings of the 39th annual Design Automation Conference
Boolean satisfiability with transitivity constraints
ACM Transactions on Computational Logic (TOCL)
Design of embedded systems: formal models, validation, and synthesis
Readings in hardware/software co-design
Formal Verification of Out-of-Order Execution with Incremental Flushing
Formal Methods in System Design
Formal Methods in System Design
Multiway Decision Graphs for Automated Hardware Verification
Formal Methods in System Design
Effectiveness of Microarchitecture Test Program Generation
IEEE Design & Test
Developing Architectural Platforms: A Disciplined Approach
IEEE Design & Test
Verifying the FM9801 Microarchitecture
IEEE Micro
BDD Based Procedures for a Theory of Equality with Uninterpreted Functions
Formal Methods in System Design
Algebraic Models of Superscalar Microprocessor Implementations: A Case Study
Proceedings of the ESPRIT Working Group 8533 on Prospects for Hardware Foundations: NADA - New Hardware Design Methods, Survey Chapters
Logical Relations in Circuit Verification
ASIAN '99 Proceedings of the 5th Asian Computing Science Conference on Advances in Computing Science
Formal Verification of Descriptions with Distinct Order of Memory Operations
ASIAN '99 Proceedings of the 5th Asian Computing Science Conference on Advances in Computing Science
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Verification of Data-Insensitive CIrcuits: An In-Order-Retirement Case Study
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Relating Multi-step and Single-Step Microprocessor Correctness Statements
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Modeling and Verification of Out-of-Order Microprocessors in UCLID
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Symbolic Functional Evaluation
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
Verified Optimizations for the Intel IA-64 Architecture
TPHOLs '00 Proceedings of the 13th International Conference on Theorem Proving in Higher Order Logics
Formal Verification of Explicitly Parallel Microprocessors
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Formal Verification of Designs with Complex Control by Symbolic Simulation
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Verification of Infinite State Systems by Compositional Model Checking
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
A Framework for Microprocessor Correctness Statements
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
TABLEAUX '99 Proceedings of the International Conference on Automated Reasoning with Analytic Tableaux and Related Methods
Deciding Equality Formulas by Small Domains Instantiations
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Automatic Verification of Combinatorial and Pipelined FFT
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Validation of Pipelined Processor Designs Using Esterel Tools: A Case Study
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Parameterized Verification with Automatically Computed Inductive Assertions
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Microarchitecture Verification by Compositional Model Checking
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
A Fault Tolerant Approach to Microprocessor Design
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
Formal Verification of a Reconfigurable Microprocessor
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Verifying a Simple Pipelined Microprocessor Using Maude
WADT '01 Selected papers from the 15th International Workshop on Recent Trends in Algebraic Development Techniques
Range Allocation for Equivalence Logic
FST TCS '01 Proceedings of the 21st Conference on Foundations of Software Technology and Theoretical Computer Science
Exploiting Positive Equality in a Logic of Equality with Uninterpreted Functions
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Finite Instantiations in Equivalence Logic with Uninterpreted Functions
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Journal of Symbolic Computation
A hybrid SAT-based decision procedure for separation logic with uninterpreted functions
Proceedings of the 40th annual Design Automation Conference
Polynomial Fairness and Liveness
CSFW '02 Proceedings of the 15th IEEE workshop on Computer Security Foundations
Si-Emulation: System Verification Using Simulation and Emulation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Systematic Formal Verification of Interpreters
ICFEM '97 Proceedings of the 1st International Conference on Formal Engineering Methods
Formal Verification of a Complex Pipelined Processor
Formal Methods in System Design
A rewriting approach to satisfiability procedures
Information and Computation - RTA 2001
Counterexample-guided abstraction refinement for symbolic model checking
Journal of the ACM (JACM)
A Practical Methodology for Verifying Pipelined Microarchitectures
IEEE Design & Test
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Graph-Based Functional Test Program Generation for Pipelined Processors
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Modeling and validation of pipeline specifications
ACM Transactions on Embedded Computing Systems (TECS)
Efficient formal verification of pipelined processors with instruction queues
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Automatic abstraction and verification of verilog models
Proceedings of the 41st annual Design Automation Conference
Verifying a gigabit ethernet switch using SMV
Proceedings of the 41st annual Design Automation Conference
A general decomposition strategy for verifying register renaming
Proceedings of the 41st annual Design Automation Conference
Efficient translation of boolean formulas to CNF in formal verification of microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Using positive equality to prove liveness for pipelined microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Linking Simulation with Formal Verification at a Higher Level
IEEE Design & Test
Verification of Embedded Memory Systems using Efficient Memory Modeling
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Refinement Maps for Efficient Verification of Processor Models
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A framework for systematic validation and debugging of pipeline simulators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Challenges in the Formal Verification of Complete State-of-the-Art Processors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Simplifying the design and automating the verification of pipelines with structural hazards
ACM Transactions on Design Automation of Electronic Systems (TODAES)
High-level optimization of pipeline design
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Refinement strategies for verification methods based on datapath abstraction
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Comparison of schemes for encoding unobservability in translation to SAT
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Using Abstraction for Efficient Formal Verification of Pipelined Processors with Value Prediction
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Formal Verification of Pipelined Microprocessors with Delayed Branches
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Verification of executable pipelined machines with bit-level interfaces
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A complete compositional reasoning framework for the efficient verification of pipelined machines
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Monolithic verification of deep pipelines with collapsed flushing
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Building small equality graphs for deciding equality logic with uninterpreted functions
Information and Computation
Propositional Satisfiability and Constraint Programming: A comparative survey
ACM Computing Surveys (CSUR)
Embedded software verification using symbolic execution and uninterpreted functions
International Journal of Parallel Programming
Fast congruence closure and extensions
Information and Computation
Automatic memory reductions for RTL model verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Electronic Notes in Theoretical Computer Science (ENTCS)
Generalizing DPLL and satisfiability for equalities
Information and Computation
Formal techniques for SystemC verification
Proceedings of the 44th annual Design Automation Conference
Memory modeling in ESL-RTL equivalence checking
Proceedings of the 44th annual Design Automation Conference
Journal of Computer Security - Special issue on CSFW15
Predicate abstraction with indexed predicates
ACM Transactions on Computational Logic (TOCL)
Semantics-preserving multitask implementation of synchronous programs
ACM Transactions on Embedded Computing Systems (TECS)
Automatic verification of safety and liveness for pipelined machines using WEB refinement
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Model checking transactional memories
Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation
Pre-RTL formal verification: an intel experience
Proceedings of the 45th annual Design Automation Conference
Testing diagnostics of modern microprocessors with the use of functional models
Automation and Remote Control
The Challenge of Hardware-Software Co-verification
Verified Software: Theories, Tools, Experiments
Getting Formal Verification into Design Flow
FM '08 Proceedings of the 15th international symposium on Formal Methods
A New Approach for the Construction of Multiway Decision Graphs
Proceedings of the 5th international colloquium on Theoretical Aspects of Computing
ATVA '08 Proceedings of the 6th International Symposium on Automated Technology for Verification and Analysis
Reveal: A Formal Verification Tool for Verilog Designs
LPAR '08 Proceedings of the 15th International Conference on Logic for Programming, Artificial Intelligence, and Reasoning
EufDpll - A Tool to Check Satisfiability of Equality Logic Formulas
Electronic Notes in Theoretical Computer Science (ENTCS)
Modelling and verification of superscalar Micro-architectures functional approach
ICCOMP'08 Proceedings of the 12th WSEAS international conference on Computers
A write-based solver for SAT modulo the theory of arrays
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Word-level sequential memory abstraction for model checking
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Symbolic program analysis using term rewriting and generalization
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
A refinement-based compositional reasoning framework for pipelined machine verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Integrated verification approach during ADL-driven processor design
Microelectronics Journal
ICTAC '09 Proceedings of the 6th International Colloquium on Theoretical Aspects of Computing
A generic implementation model for the formal verification of networks-on-chips
Proceedings of the Eighth International Workshop on the ACL2 Theorem Prover and its Applications
Encoding RTL Constructs for MathSAT: a Preliminary Report
Electronic Notes in Theoretical Computer Science (ENTCS)
Reduced Functional Consistency of Uninterpreted Functions
Electronic Notes in Theoretical Computer Science (ENTCS)
Building small equality graphs for deciding equality logic with uninterpreted functions
Information and Computation
Equational binary decision diagrams
LPAR'00 Proceedings of the 7th international conference on Logic for programming and automated reasoning
Algebraic models of simultaneous multithreaded and multi-core processors
CALCO'07 Proceedings of the 2nd international conference on Algebra and coalgebra in computer science
Challenges in satisfiability modulo theories
RTA'07 Proceedings of the 18th international conference on Term rewriting and applications
Simulation vs. formal: absorb what is useful; reject what is useless
HVC'07 Proceedings of the 3rd international Haifa verification conference on Hardware and software: verification and testing
A method for debugging of pipelined processors in formal verification by correspondence checking
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Research Letters in Signal Processing
Method for formal verification of soft-error tolerance mechanisms in pipelined microprocessors
ICFEM'10 Proceedings of the 12th international conference on Formal engineering methods and software engineering
Automatic formal verification of reconfigurable DSPs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Optimization techniques for verification of out-of-order execution machines
Journal of Electrical and Computer Engineering
NuMDG: a new tool for multiway decision graphs construction
Journal of Computer Science and Technology - Special issue on natural language processing
Automated formal verification of processors based on architectural models
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Monitoring aspects for the customization of automatically generated code for big-step models
Proceedings of the 10th ACM international conference on Generative programming and component engineering
ICFEM'11 Proceedings of the 13th international conference on Formal methods and software engineering
Decision procedures for SAT, SAT modulo theories and beyond. the barcelogictools
LPAR'05 Proceedings of the 12th international conference on Logic for Programming, Artificial Intelligence, and Reasoning
Pipelined microprocessors optimization and debugging
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Formally defining and verifying master/slave speculative parallelization
FM'05 Proceedings of the 2005 international conference on Formal Methods
Automatic formal verification of multithreaded pipelined microprocessors
Proceedings of the International Conference on Computer-Aided Design
A BDD-Representation for the logic of equality and uninterpreted functions
MFCS'05 Proceedings of the 30th international conference on Mathematical Foundations of Computer Science
Yet another decision procedure for equality logic
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
The algebra of equality proofs
RTA'05 Proceedings of the 16th international conference on Term Rewriting and Applications
CALCO'05 Proceedings of the First international conference on Algebra and Coalgebra in Computer Science
Automatic formal verification of liveness for pipelined processors with multicycle functional units
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Counterexample guided invariant discovery for parameterized cache coherence verification
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
A parameterized benchmark suite of hard pipelined-machine-verification problems
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Learning conditional abstractions
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Desynchronization: design for verification
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
From propositional satisfiability to satisfiability modulo theories
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
SAT-Based verification methods and applications in hardware verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Building efficient decision procedures on top of SAT solvers
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Refinement and theorem proving
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Symbolic bounded conformance checking of model programs
PSI'09 Proceedings of the 7th international Andrei Ershov Memorial conference on Perspectives of Systems Informatics
Equivalence checking for behaviorally synthesized pipelines
Proceedings of the 49th Annual Design Automation Conference
Model checking and abstraction to the aid of parameterized systems (a survey)
Computer Languages, Systems and Structures
Formal Verification and Debugging of Precise Interrupts on High Performance Microprocessors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Formal Analysis of SystemC Designs in Process Algebra
Fundamenta Informaticae
Verification of computer switching networks: an overview
ATVA'12 Proceedings of the 10th international conference on Automated Technology for Verification and Analysis
| Hi-index | 0.00 |