Formal verification of pipeline control using controlled token nets and abstract interpretation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A new verification methodology for complex pipeline behavior
Proceedings of the 38th annual Design Automation Conference
Verifying the FM9801 Microarchitecture
IEEE Micro
Reasoning About Pipelines with Structural Hazards
TPCD '94 Proceedings of the Second International Conference on Theorem Provers in Circuit Design - Theory, Practice and Experience
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Proceedings of the conference on Design, automation and test in Europe
Correct-by-construction microarchitectural pipelining
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Policies of System Level Pipeline Modeling
Electronic Notes in Theoretical Computer Science (ENTCS)
A SystemC library for specifying pipeline abstractions
Microprocessors & Microsystems
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This article describes a technique that simplifies the design of pipelined circuits automates the specification and verification of structural-hazard and datapath correctness properties for pipelined circuits. The technique is based upon a template for pipeline stages, a control-circuit cell library, a decomposition of structural hazard and datapath correctness into a collection of simple properties, and a prototype design tool that generates verification scripts for use by external tools. Our case studies include scalar and superscalar implementations of a 32-bit OpenRISC integer microprocessor.