Techniques for verifying superscalar microprocessors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Symbolic Model Checking
Formal Semantics for VHDL
ACL2 Theorems About Commercial Microprocessors
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Trace Table Based Approach for Pipeline Microprocessor Verification
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Verification of an Implementation of Tomasulo's Algorithm by Compositional Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Processor Verification with Precise Exeptions and Speculative Execution
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
The Semantic Challenge of Verilog HDL
LICS '95 Proceedings of the 10th Annual IEEE Symposium on Logic in Computer Science
Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories
Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories
Hardware Modeling Using Function Encapsulation
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Formal Verification of a Complex Pipelined Processor
Formal Methods in System Design
A general decomposition strategy for verifying register renaming
Proceedings of the 41st annual Design Automation Conference
Challenges in the Formal Verification of Complete State-of-the-Art Processors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Simplifying the design and automating the verification of pipelines with structural hazards
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Formal techniques for SystemC verification
Proceedings of the 44th annual Design Automation Conference
Automatic verification of external interrupt behaviors for microprocessor design
Proceedings of the 44th annual Design Automation Conference
Optimization techniques for verification of out-of-order execution machines
Journal of Electrical and Computer Engineering
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Designers use formal logic and a theorem prover to verify that a complex microarchitecture always implements its instruction set correctly. Hardware verification accounts for a considerable portion of the costs in the microprocessor design process. Traditionally, designers have verified microprocessor designs using simulation techniques that help find most design faults. However, simulation never guarantees the correct operation of the final product. Some design faults are very difficult to detect by simulation; they may slip through the verification process into manufactured chips, raising costs. We believe that verification costs can be reduced by the judicious application of formal methods, which should lower the overall costs of design.