A general decomposition strategy for verifying register renaming

Authors:
Hazem I. Shehata;Mark D. Aagaard
Affiliations:
University of Waterloo, Waterloo, Canada;University of Waterloo, Waterloo, Canada
Venue:
Proceedings of the 41st annual Design Automation Conference
Year:
2004

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Abstract

This paper describes a strategy for verifying data-hazard correctness of out-of-order processors that implement register-renaming. We define a set of predicates to characterize register-renaming techniques and provide a set of model-checking obligations that are sufficient to guarantee that a register-renaming technique satisfies data-hazard correctness. We demonstrate how two register renaming techniques (retirement-register-file and dual-RAT) instantiate our predicates, and present model checking results for the Dual-RAT technique, which is based on the Intel Pentium 4 processor.