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Rewriting rules and Positive Equality [4] are combined in anautomatic way in order to formally verify out-of-order proces-sorsthat have a Reorder Buffer, and can issue/retire multipleinstructions per clock cycle. Only register-register instructionsare implemented, and can be executed out-of-order, as soon astheir data operands can be either read from the Register File, orforwarded as results of instructions ahead in program order inthe Reorder Buffer. The verification is based on the Burch andDill correctness criterion [6]. Rewriting rules are used to provethe correct execution of instructions that are initially in the Reor-derBuffer, and to remove them from the correctness formula.Positive Equality is then employed to prove the correct executionof newly fetched instructions. The rewriting rules resulted in upto 5 orders of magnitude speedup, compared to using PositiveEquality alone. That made it possible to formally verify proces-sorswith up to 1,500 instructions in the Reorder Buffer, andissue/retire widths of up to 128 instructions per clock cycle.