Techniques for verifying superscalar microprocessors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
ACM Transactions on Computational Logic (TOCL)
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Boolean satisfiability with transitivity constraints
ACM Transactions on Computational Logic (TOCL)
The small model property: how small can it be?
Information and Computation
Itanium Processor Microarchitecture
IEEE Micro
BDD Based Procedures for a Theory of Equality with Uninterpreted Functions
Formal Methods in System Design
Bit-Level Abstraction in the Verfication of Pipelined Microprocessors by Correspondence Checking
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Relating Multi-step and Single-Step Microprocessor Correctness Statements
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Formal Verification of VLIW Microprocessors with Speculative Execution
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Journal of Symbolic Computation
Experience with Term Level Modeling and Verification of the M*Core microprocessor Core.
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Efficient translation of boolean formulas to CNF in formal verification of microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Using positive equality to prove liveness for pipelined microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Comparative Study of Strategies for Formal Verification of High-Level Processors
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Comparison of schemes for encoding unobservability in translation to SAT
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Using Abstraction for Efficient Formal Verification of Pipelined Processors with Value Prediction
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Formal Verification of Pipelined Microprocessors with Delayed Branches
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
Journal of Signal Processing Systems
IEEE Spectrum
A lightweight component caching scheme for satisfiability solvers
SAT'07 Proceedings of the 10th international conference on Theory and applications of satisfiability testing
A method for debugging of pipelined processors in formal verification by correspondence checking
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Method for formal verification of soft-error tolerance mechanisms in pipelined microprocessors
ICFEM'10 Proceedings of the 12th international conference on Formal engineering methods and software engineering
Automatic formal verification of reconfigurable DSPs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Automatic formal verification of liveness for pipelined processors with multicycle functional units
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Automatic formal verification of multithreaded pipelined microprocessors
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
We compare two approaches for efficient formal verification of the integration of pipelined processor cores with arrays of reconfigurable functional units. The processors are modeled at a high level of abstraction, using a subset of Verilog, in a way that allows us to exploit the property of Positive Equality that results in significant simplifications of the solution space, and orders of magnitude speedup relative to previous methods. The presented techniques allow us to formally verify the integration of pipelined processors, including complex Digital Signal Processors (DSPs), with arrays of reconfigurable functional units of any size, where the reconfigurable functional units have any design, and for any topology of the connections between them. Such architectures are becoming increasingly used because of their much higher performance and reduced power consumption relative to conventional processors. One of the compared two approaches, which abstracts the entire array of reconfigurable functional units, results in at least 3 orders of magnitude speedup relative to the other approach that models the exact number of reconfigurable functional units and abstracts the design of each and the network that connects them, such that the speedup is increasing with the size of the array. To the best of our knowledge, this is the first work on automatic formal verification of pipelined processors with arrays of reconfigurable functional units.