A Structure-preserving Clause Form Translation
Journal of Symbolic Computation
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Chaff: engineering an efficient SAT solver
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Dynamic detection and removal of inactive clauses in SAT with application in image computation
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Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver
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Computer architecture: a quantitative approach
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CP '02 Proceedings of the 8th International Conference on Principles and Practice of Constraint Programming
Formal Verification of VLIW Microprocessors with Speculative Execution
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Journal of Symbolic Computation
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HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
Probing-Based Preprocessing Techniques for Propositional Satisfiability
ICTAI '03 Proceedings of the 15th IEEE International Conference on Tools with Artificial Intelligence
Managing Don't Cares in Boolean Satisfiability
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Efficient translation of boolean formulas to CNF in formal verification of microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
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IJCAI'01 Proceedings of the 17th international joint conference on Artificial intelligence - Volume 1
CirCUs: a hybrid satisfiability solver
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Exploiting hierarchy and structure to efficiently solve graph coloring as SAT
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Comparison of Boolean satisfiability encodings on FPGA detailed routing problems
Proceedings of the conference on Design, automation and test in Europe
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Proceedings of the Conference on Design, Automation and Test in Europe
Method for formal verification of soft-error tolerance mechanisms in pipelined microprocessors
ICFEM'10 Proceedings of the 12th international conference on Formal engineering methods and software engineering
Automatic formal verification of reconfigurable DSPs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
ICFEM'11 Proceedings of the 13th international conference on Formal methods and software engineering
Automatic formal verification of multithreaded pipelined microprocessors
Proceedings of the International Conference on Computer-Aided Design
Solving quantified boolean formulas with circuit observability don't cares
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
Automated design debugging in a testbench-based verification environment
Microprocessors & Microsystems
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Compared are seven schemes for encoding unobservability of logic blocks in Boolean-to-CNF translation. Four of the schemes are based on merging of logic blocks with adjacent gates toward the primary output. Two are based on using CNF unobservability variables to encode the unobservability of logic blocks. Also explored is a hybrid scheme. Encoding the unobservability of logic blocks accelerated the SAT-solving of Boolean formulas from formal verification of complex micro-processors, while allowing us to use a conventional CNF-based SAT-solver. On unsatisfiable CNF formulas, best was the strategy of merging logic blocks with adjacent gates on the only path from the block output to the primary output, with a resulting speedup of up to 16x for CNF formulas with hundreds of thousands of variables, millions of clauses, and tens of millions of literals. Furthermore, the speedup is relative to an already very efficient Boolean-to-CNF translation. On satisfiable CNF formulas, best was the strategy of merging logic blocks with leaf gates and with adjacent gates on the only path to the primary output, as well as exploiting the polarity of gates and logic blocks to reduce the number of their clauses. The presented optimizations are general and applicable to other classes of Boolean formulas.