A machine program for theorem-proving
Communications of the ACM
Checking equivalence for partial implementations
Proceedings of the 38th annual Design Automation Conference
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Dynamic detection and removal of inactive clauses in SAT with application in image computation
Proceedings of the 38th annual Design Automation Conference
Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver
Proceedings of the 39th annual Design Automation Conference
Efficient conflict driven learning in a boolean satisfiability solver
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Lemma and Model Caching in Decision Procedures for Quantified Boolean Formulas
TABLEAUX '02 Proceedings of the International Conference on Automated Reasoning with Analytic Tableaux and Related Methods
Towards a Symmetric Treatment of Satisfaction and Conflicts in Quantified Boolean Formula Evaluation
CP '02 Proceedings of the 8th International Conference on Principles and Practice of Constraint Programming
Conflict driven learning in a quantified Boolean Satisfiability solver
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Learning for quantified boolean logic satisfiability
Eighteenth national conference on Artificial intelligence
Managing Don't Cares in Boolean Satisfiability
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A Circuit SAT Solver With Signal Correlation Guided Learning
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Space-Efficient Bounded Model Checking
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Considering Circuit Observability Don't Cares in CNF Satisfiability
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Comparison of schemes for encoding unobservability in translation to SAT
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
AAAI'05 Proceedings of the 20th national conference on Artificial intelligence - Volume 1
Constructing conditional plans by a theorem-prover
Journal of Artificial Intelligence Research
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Beyond CNF: A Circuit-Based QBF Solver
SAT '09 Proceedings of the 12th International Conference on Theory and Applications of Satisfiability Testing
Nenofex: expanding NNF for QBF solving
SAT'08 Proceedings of the 11th international conference on Theory and applications of satisfiability testing
Leveraging dominators for preprocessing QBF
Proceedings of the Conference on Design, Automation and Test in Europe
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Traditionally the propositional part of a Quantified Boolean Formula (QBF) instance has been represented using a conjunctive normal form (CNF). As with propositional satisfiability (SAT), this is motivated by the efficiency of this data structure. However, in many cases, part of or the entire propositional part of a QBF instance can often be represented as a combinational logic circuit. In a logic circuit, the limited observability of the internal signals at the circuit outputs may make their assignments irrelevant for specific assignments of values to other signals in the circuit. This circuit observability don't care (ODC) information has been used to advantage in circuit based SAT solvers. A CNF encoding of the circuit, however, does not capture the signal direction and this limited observability, and thus cannot directly take advantage of this. However, recently it has been shown that this don't care information can be encoded in the CNF description and taken advantage of in a DPLL based SAT solver by modifying the decision heuristics/Boolean constraint propagation/conflict-driven-learning to account for these don't cares. Thus far, however, the use of these don't cares in the CNF encoding has not been explored for QBF solvers. In this paper, we examine how this can be done for QBF solvers as well as evaluate its practical benefits through experimentation. We have developed and implemented the usage of circuit ODCs in various parts of the DPLL-based procedure of the Quaffle QBF solver. We show that DPLL search based QBF solvers can use circuit ODC information to detect satisfying branches earlier during search and make satisfiability directed learning more effective. Our experiments demonstrate that significant performance gain can be obtained by considering circuit ODCs in checking the satisfiability of QBFs.