GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
A machine program for theorem-proving
Communications of the ACM
Circuit-based Boolean Reasoning
Proceedings of the 38th annual Design Automation Conference
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
SATO: An Efficient Propositional Prover
CADE-14 Proceedings of the 14th International Conference on Automated Deduction
The Quest for Efficient Boolean Satisfiability Solvers
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
SAT and ATPG: Boolean engines for formal hardware verification
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A signal correlation guided ATPG solver and its applications for solving difficult industrial cases
Proceedings of the 40th annual Design Automation Conference
Learning from BDDs in SAT-based bounded model checking
Proceedings of the 40th annual Design Automation Conference
Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Managing Don't Cares in Boolean Satisfiability
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Refining the SAT decision ordering for bounded model checking
Proceedings of the 41st annual Design Automation Conference
Iterative Abstraction using SAT-based BMC with Proof Analysis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Efficient translation of boolean formulas to CNF in formal verification of microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A Circuit SAT Solver With Signal Correlation Guided Learning
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Verification of Embedded Memory Systems using Efficient Memory Modeling
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
An Efficient Sequential SAT Solver With Improved Search Strategies
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Considering Circuit Observability Don't Cares in CNF Satisfiability
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Beyond safety: customized SAT-based model checking
Proceedings of the 42nd annual Design Automation Conference
Unrestricted vs restricted cut in a tableau method for Boolean circuits
Annals of Mathematics and Artificial Intelligence
Functional test generation based on word-level SAT
Journal of Systems Architecture: the EUROMICRO Journal
DAG-aware circuit compression for formal verification
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Efficient SAT-based unbounded symbolic model checking using circuit cofactoring
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Comparison of schemes for encoding unobservability in translation to SAT
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Propositional Satisfiability and Constraint Programming: A comparative survey
ACM Computing Surveys (CSUR)
Specifying and solving Boolean constraint problems in relational databases: a case study
Proceedings of the 44th annual Southeast regional conference
Program slicing for declarative models
ACM SIGSOFT Software Engineering Notes
Improvements to combinational equivalence checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Kato: A Program Slicing Tool for Declarative Specifications
ICSE '07 Proceedings of the 29th international conference on Software Engineering
QuteSAT: a robust circuit-based SAT solver for complex circuit structure
Proceedings of the conference on Design, automation and test in Europe
Preprocessing for controlled query evaluation with availability policy
Journal of Computer Security - 20th Annual IFIP WG 11.3 Working Conference on Data and Applications Security (DBSec'06)
Constraint Prioritization for Efficient Analysis of Declarative Models
FM '08 Proceedings of the 15th international symposium on Formal Methods
Whispec: white-box testing of libraries using declarative specifications
LCSD '07 Proceedings of the 2007 Symposium on Library-Centric Software Design
Efficient Decision Procedure for Bounded Integer Non-linear Operations Using SMT($\mathcal{LIA}$)
HVC '08 Proceedings of the 4th International Haifa Verification Conference on Hardware and Software: Verification and Testing
Verification Techniques for System-Level Design
Verification Techniques for System-Level Design
Hybrid BDD and All-SAT Method for Model Checking
Languages: From Formal to Natural
On the power of top-down branching heuristics
AAAI'08 Proceedings of the 23rd national conference on Artificial intelligence - Volume 1
IJCAI'07 Proceedings of the 20th international joint conference on Artifical intelligence
Efficient SAT solving for non-clausal formulas using DPLL, graphs, and watched cuts
Proceedings of the 46th Annual Design Automation Conference
Combining SAT Methods with Non-Clausal Decision Heuristics
Electronic Notes in Theoretical Computer Science (ENTCS)
An Incremental Algorithm to Check Satisfiability for Bounded Model Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
3-valued circuit SAT for STE with automatic refinement
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
Simulation vs. formal: absorb what is useful; reject what is useless
HVC'07 Proceedings of the 3rd international Haifa verification conference on Hardware and software: verification and testing
Sechecker: a sequential equivalence checking framework based on K th invariants
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Propelling SAT and SAT-based BMC using careset
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Transformations into normal forms for quantified circuits
SAT'11 Proceedings of the 14th international conference on Theory and application of satisfiability testing
On finding an inference-proof complete database for controlled query evaluation
DBSEC'06 Proceedings of the 20th IFIP WG 11.3 working conference on Data and Applications Security
CirCUs: a hybrid satisfiability solver
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Optimizations for compiling declarative models into boolean formulas
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
DiVer: SAT-based model checking platform for verifying large scale systems
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
A non-prenex, non-clausal QBF solver with game-state learning
SAT'10 Proceedings of the 13th international conference on Theory and Applications of Satisfiability Testing
Satisfiability checking of non-clausal formulas using general matings
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
Solving quantified boolean formulas with circuit observability don't cares
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
SAT-Based verification methods and applications in hardware verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Automated reencoding of boolean formulas
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
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We propose Satisfiability Checking (SAT) techniques that lead to a consistent performance improvement of up to 3x over state-of-the-art SAT solvers like Chaff on important problem domains in VLSI CAD. We observe that in circuit oriented applications like ATPG and verification, different software engineering techniques are required for the portions of the formula corresponding to learnt clauses compared to the original formula. We demonstrate that by employing the same innovations as in advanced CNF-based SAT solvers, but in a hybrid approach where these two portions of the formula are represented differently and processed separately, it is possible to obtain the consistently highest performing SAT solver for circuit oriented problem domains. We also present controlled experiments to highlight where these gains come from. Once it is established that the hybrid approach is faster, it becomes possible to apply low overhead circuit-based heuristics that would be unavailable in the CNF domain for greater speedup.