Unrestricted vs restricted cut in a tableau method for Boolean circuits

  • Authors:

  • Matti Järvisalo;Tommi Junttila;Ilkka Niemelä

  • Affiliations:

  • Helsinki University of Technology, Laboratory for Theoretical Computer Science, Finland FI-02015 TKK;Helsinki University of Technology, Laboratory for Theoretical Computer Science, Finland FI-02015 TKK;Helsinki University of Technology, Laboratory for Theoretical Computer Science, Finland FI-02015 TKK

  • Venue:
  • Annals of Mathematics and Artificial Intelligence
  • Year:
  • 2005

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Abstract

This paper studies the relative efficiency of variations of a tableau method for Boolean circuit satisfiability checking. The considered method is a nonclausal generalisation of the Davis---Putnam---Logemann---Loveland (DPLL) procedure to Boolean circuits. The variations are obtained by restricting the use of the cut (splitting) rule in several natural ways. It is shown that the more restricted variations cannot polynomially simulate the less restricted ones. For each pair of methods T, T驴, an infinite family $\{\mathcal{C}_{n}\}$ of circuits is devised for which T has polynomial size proofs while in T驴 the minimal proofs are of exponential size w.r.t. n, implying exponential separation of T and T驴 w.r.t. n. The results also apply to DPLL for formulas in conjunctive normal form obtained from Boolean circuits by using Tseitin's translation. Thus DPLL with the considered cut restrictions, such as allowing splitting only on the variables corresponding to the input gates, cannot polynomially simulate DPLL with unrestricted splitting.