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Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Combinational equivalence checking using satisfiability and recursive learning
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A Computing Procedure for Quantification Theory
Journal of the ACM (JACM)
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques
Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
Using CSP look-back techniques to solve real-world SAT instances
AAAI'97/IAAI'97 Proceedings of the fourteenth national conference on artificial intelligence and ninth conference on Innovative applications of artificial intelligence
Solving satisfiability in combinational circuits with backtrack search and recursive learning
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Unrestricted vs restricted cut in a tableau method for Boolean circuits
Annals of Mathematics and Artificial Intelligence
Improvements to combinational equivalence checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Interactive presentation: A shift register based clause evaluator for reconfigurable SAT solver
Proceedings of the conference on Design, automation and test in Europe
Sechecker: a sequential equivalence checking framework based on K th invariants
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA based accelerator for 3-SAT conflict analysis in SAT solvers
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
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Editor's note: As EDA evolves, researchers continue to find modeling tools to solve problems of test generation, design verification, logic, and physical synthesis, among others. One such modeling tool is Boolean satisfiability (SAT), which has very broad applicability in EDA. The authors review modern SAT algorithms, show how these algorithms can account for structural information in combinational circuits, and explain what recursive learning can add to SAT.驴Marcelo Lubaszewski, Federal University of Rio Grande do Sul