FPGA based accelerator for 3-SAT conflict analysis in SAT solvers

Authors:
Mona Safar;M. Watheq El-Kharashi;Ashraf Salem
Affiliations:
Computer and Systems Department, Ain Shams University, Cairo, Egypt;University of Victoria, Victoria, Canada;Mentor Graphics Egypt, Cairo, Egypt
Venue:
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Year:
2005

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Abstract

We present an FPGA-based accelerator for 3-SAT clause evaluation and conflict diagnosis and propose an approach to incorporate it in solving the Combinational Equivalence Checking problem. SAT binary clauses are mapped onto an implication graph and the ternary clauses are kept in an indexed clause database and mapped into the clause evaluator and conflict analyzer on FPGA.