Instruction generation for hybrid reconfigurable systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Instance-Specific Accelerators for Minimum Covering
The Journal of Supercomputing
Reconfigurable Hardware SAT Solvers: A Survey of Systems
IEEE Transactions on Computers
A practical reconfigurable hardware accelerator for Boolean satisfiability solvers
Proceedings of the 45th annual Design Automation Conference
PN code acquisition using Boolean satisfiability techniques
WCNC'09 Proceedings of the 2009 IEEE conference on Wireless Communications & Networking Conference
Designing an efficient hardware implication accelerator for SAT solving
SAT'08 Proceedings of the 11th international conference on Theory and applications of satisfiability testing
Relieving capacity limits on FPGA-based SAT-solvers
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
FPGA based accelerator for 3-SAT conflict analysis in SAT solvers
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
A hardware relaxation paradigm for solving NP-hard problems
VoCS'08 Proceedings of the 2008 international conference on Visions of Computer Science: BCS International Academic Conference
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The issues of software compute time and complexity are very important in current computer-aided design (CAD) tools. As field-programmable gate array (FPGA) speeds and densities increase, the opportunity for effective hardware accelerators built from FPGA technology has opened up. This paper describes and evaluates a formula-specific method for implementing Boolean satisfiability solver circuits in configurable hardware. That is, using a template generator, we create circuits specific to the problem instance to be solved. This approach yields impressive runtime speedups of up to several hundred times compared to the software approaches. The high performance comes from realizing fine-grained parallelism inherent in the clause evaluation and implication and from direct mapping of Boolean relations into logic gates. Our implementation uses a commercially available hardware system for proof of concept. This system yields more than 100 times run-time speedup on many problems, even though the clock rate of the hardware is 100 times slower than that of the workstation running the software solver. While the time to compile the solver circuit to configurable hardware can he quite long on current platforms (20-40 min per chip), this paper discusses new approaches to overcome this compilation overhead. More broadly, we view this work as a case study in the burgeoning domain of high performance configurable computing. Our approach realizes large amount of fine-grained parallelism, and has broad applications in the very large scale integration CAD area