DAC '96 Proceedings of the 33rd annual Design Automation Conference
The algorithm design manual
DAC '98 Proceedings of the 35th annual Design Automation Conference
A Computing Procedure for Quantification Theory
Journal of the ACM (JACM)
Solving covering problems using LPR-based lower bounds
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Solving satisfiability problems using reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
A bitstream reconfigurable FPGA implementation of the WSAT algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Object-oriented domain specific compilers for programming FPGA's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
A SAT Solver Using Reconfigurable Hardware and Virtual Logic
Journal of Automated Reasoning
Domain Specific Mapping for Solving Graph Problems on Reconfigurable Devices
Proceedings of the 11 IPPS/SPDP'99 Workshops Held in Conjunction with the 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing
Satisfiability on reconfigurable hardware
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Acceleration of Satisfiability Algorithms by Reconfigurable Hardware
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
A Runtime Reconfigurable Implementation of the GSAT Algorithm
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
A Methodological Approach to Implement CSP on FPGA
RSP '99 Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping
Using configurable computing to accelerate Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents the acceleration of minimum-cost covering problems by instance-specific hardware. First, we formulate the minimum-cost covering problem and discuss a branch & bound algorithm to solve it. Then we describe instance-specific hardware architectures that implement branch & bound in 3-valued logic and use reduction techniques similar to those found in software solvers. We further present prototypical accelerator implementations and a corresponding design tool flow. Our experiments reveal significant raw speedups up to five orders of magnitude for a set of smaller unate covering problems. Provided that hardware compilation times can be reduced, we conclude that instance-specific acceleration of hard minimum-cost covering problems will lead to substantial overall speedups.