Partially Reconfigurable Cores for Xilinx Virtex
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Instance-Specific Accelerators for Minimum Covering
The Journal of Supercomputing
Reconfigurable Hardware SAT Solvers: A Survey of Systems
IEEE Transactions on Computers
Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey
Journal of VLSI Signal Processing Systems
H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Run-time reconfigurable systems for digital signal processing applications: a survey
Journal of VLSI Signal Processing Systems
A fast SAT solver algorithm best suited to reconfigurable hardware
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
An Approach for Solving Large SAT Problems on FPGA
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
An FPGA-Based parallel accelerator for matrix multiplications in the newton-raphson method
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
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A field programmable gate array (FPGA) implementation of a coprocessor which uses the WSAT algorithm to solve Boolean satisfiability problems is presented. The input is a SAT problem description file from which a software program directly generates a problem-specific circuit design which can be downloaded to a Xilinx Virtex FPGA device and executed to find a solution. On an XCV300, problems of 50 variables and 170 clauses can be solved. Compared with previous approaches, it avoids the need for resynthesis, placement, and routing for different constraints. Our coprocessor is eminently suitable for embedded applications where energy, weight and real-time response are of concern.