Secure Distributed Constraint Satisfaction: Reaching Agreement without Revealing Private Information
CP '02 Proceedings of the 8th International Conference on Principles and Practice of Constraint Programming
Instance-Specific Accelerators for Minimum Covering
The Journal of Supercomputing
Reconfigurable Hardware SAT Solvers: A Survey of Systems
IEEE Transactions on Computers
A software/reconfigurable hardware SAT solver
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Secure distributed constraint satisfaction: reaching agreement without revealing private information
Artificial Intelligence - Special issue: Distributed constraint satisfaction
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SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Secure distributed constraint satisfaction: reaching agreement without revealing private information
Artificial Intelligence - Special issue: Distributed constraint satisfaction
Computer Languages, Systems and Structures
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SAT'08 Proceedings of the 11th international conference on Theory and applications of satisfiability testing
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Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
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This paper reports on an innovative approach for solving satisfiability problems for propositional formulas in conjunctive normal form (SAT) by creating a logic circuit that is specialized to solve each problem instance on field programmable gate arrays (FPGAs). This approach has become feasible due to recent advances in reconfigurable computing and has opened up an exciting new research field in algorithm design. SAT is an important subclass of constraint satisfaction problems, which can formalize a wide range of application problems. We have developed a series of algorithms that are suitable for a logic circuit implementation, including an algorithm whose performance is equivalent to the Davis-Putnam procedure with powerful dynamic variable ordering. Simulation results show that this method can solve a hard random 3-SAT problem with 400 variables within 1.6 min at a clock rate of 10 MHz. Faster speeds can be obtained by increasing the clock rate. Furthermore, we have actually implemented a 128-variable 256-clause problem instance on FPGAs.