GRASP—a new search algorithm for satisfiability
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Solving satisfiability problems using reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
A SAT Solver Using Reconfigurable Hardware and Virtual Logic
Journal of Automated Reasoning
Run-time performance optimization of an FPGA-based deduction engine for SAT solvers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Acceleration of Satisfiability Algorithms by Reconfigurable Hardware
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
Reconfigurable Hardware SAT Solvers: A Survey of Systems
IEEE Transactions on Computers
A software/reconfigurable hardware SAT solver
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Configurable Hardware/Software Approach to SAT Solving
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A practical reconfigurable hardware accelerator for Boolean satisfiability solvers
Proceedings of the 45th annual Design Automation Conference
FPGA-based hardware acceleration for Boolean satisfiability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Designing an efficient hardware implication accelerator for SAT solving
SAT'08 Proceedings of the 11th international conference on Theory and applications of satisfiability testing
Using CSP look-back techniques to solve real-world SAT instances
AAAI'97/IAAI'97 Proceedings of the fourteenth national conference on artificial intelligence and ninth conference on Innovative applications of artificial intelligence
Using configurable computing to accelerate Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FPGA acceleration of enhanced boolean constraint propagation for SAT solvers
Proceedings of the International Conference on Computer-Aided Design
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FPGA-based SAT solvers have the potential to dramatically accelerate SAT solving by effectively exploiting finegrained pipeline parallelism in a manner which is not achievable with regular processors. Previous hardware-based approaches have relied on on-chip memory resources to store data which, similar to a CPU cache, are very fast, but are also very limited in size. For hardware-based SAT approaches to scale to real-world instances, it is necessary to utilise large amounts of off-chip memory. We present novel techniques for storing and retrieving SAT clauses using a custom multi-port memory interface to offchip DRAM which is connected to a processor core implemented on a medium sized FPGA on the BEE3 system. Since DRAM is slower than on-chip memory resources, the parallelisation which can be achieved is limited by memory throughput. We present the design and implementation of a new parallel architecture that tackles this problem and estimate the performance of our approach with memory benchmarks.