A massively-parallel easily-scalable satisfiability solver using reconfigurable hardware
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A Computing Procedure for Quantification Theory
Journal of the ACM (JACM)
Parallel algorithms for FPGA placement
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
A Reconfigurable multifunction computing cache architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Domain Specific Mapping for Solving Graph Problems on Reconfigurable Devices
Proceedings of the 11 IPPS/SPDP'99 Workshops Held in Conjunction with the 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing
Satisfiability on reconfigurable hardware
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Acceleration of Satisfiability Algorithms by Reconfigurable Hardware
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
Solving Boolean Satisfiability with Dynamic Hardware Configurations
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
Solving Satisfiability Problems on FPGAs
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
The MorphoSys Dynamically Reconfigurable System-on-Chip
EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
High level compilation for fine grained FPGAs
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
An FPGA-based coprocessor for ATM firewalls
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
A Run-Time Reconfigurable Engine for Image Interpolation
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Accelerating Boolean Satisfiability with Configurable Hardware
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
A Stream-Based Configurable Computing Radio Testbed
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Design methodologies for partially reconfigured systems
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Proceedings of the 1st conference on Computing frontiers
Reconfigurable Hardware SAT Solvers: A Survey of Systems
IEEE Transactions on Computers
A fast SAT solver algorithm best suited to reconfigurable hardware
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Propositional Satisfiability and Constraint Programming: A comparative survey
ACM Computing Surveys (CSUR)
Interactive presentation: A shift register based clause evaluator for reconfigurable SAT solver
Proceedings of the conference on Design, automation and test in Europe
PN code acquisition using Boolean satisfiability techniques
WCNC'09 Proceedings of the 2009 IEEE conference on Wireless Communications & Networking Conference
A hardware SAT solver using non-chronological backtracking and clause recording without overheads
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Designing an efficient hardware implication accelerator for SAT solving
SAT'08 Proceedings of the 11th international conference on Theory and applications of satisfiability testing
Relieving capacity limits on FPGA-based SAT-solvers
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
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FPGAs are a promising technology for accelerating SAT solvers. Besides their high density, fine granularity, and massive parallelism, FPGAs provide the opportunity for run-time customization of the hardware based on the given SAT instance. In this article, a parallel deduction engine is proposed for backtrack search algorithms. The performance of the deduction engine is critical to the overall performance of the algorithm because, for any moderate SAT instance, millions of implications are derived. We propose a novel approach in which p, the amount of parallelization of the engine, is fine-tuned during problem solving in order to optimize performance. Not only the hardware is initially customized based on the input instance, but it is also dynamically modified in terms of p based on the knowledge gained during solving the SAT instance. Compared with conventional deduction engines that correspond to p = 1, we demonstrate speedups in the range of 2.87 to 5.44 for several SAT instances.