A loosely coupled parallel algorithm for standard cell placement
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Architectural and physical design challenges for one-million gate FPGAs and beyond
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
FPGA and CPLD Architectures: A Tutorial
IEEE Design & Test
Parallel Simulated Annealing Algorithms for Cell Placement on Hypercube Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
ProperPLACE: A Portable Parallel Algorithm for Standard Cell Placement
Proceedings of the 8th International Symposium on Parallel Processing
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Parallel simulated annealing strategies for VLSI cell placement
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
An evaluation of parallel simulated annealing strategies with application to standard cell placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Run-time performance optimization of an FPGA-based deduction engine for SAT solvers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hardware-assisted simulated annealing with application for fast FPGA placement
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Parallel placement for field-programmable gate arrays
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
A novel approach to the placement and routing problems for field programmable gate arrays
Applied Soft Computing
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
High-quality, deterministic parallel placement for FPGAs on commodity hardware
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Static and Dynamic Memory Footprint Reduction for FPGA Routing Algorithms
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
A framework for core-level modeling and design of reconfigurable computing algorithms
Proceedings of the Third International Workshop on High-Performance Reconfigurable Computing Technology and Applications
Speeding up FPGA placement via partitioning and multithreading
International Journal of Reconfigurable Computing
Scalable and deterministic timing-driven parallel placement for FPGAs
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Efficient and Deterministic Parallel Placement for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Analyzing System-Level Information’s Correlation to FPGA Placement
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Fast FPGA CAD tools that produce high quality results has been one of the most important research issues in the FPGA domain. Simulated annealing has been the method of choice for placement. However, simulated annealing is a very compute-intensive method. In our present work we investigate a range of parallelization strategies to speedup simulated annealing with application to placement for FPGA. We present experimental results obtained by applying the different parallelization strategies to the Versatile Place and Route (VPR) Tool, implemented on an SGI Origin shared memory multi-processor and an IBM-SP2 distributed memory multi-processor. The results show the tradeoff between execution time and quality of result for the different parallelization strategies.