PARASPICE: a parallel circuit simulator for shared-memory multiprocessors
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A loosely coupled parallel algorithm for standard cell placement
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Threads primer: a guide to multithreaded programming
Threads primer: a guide to multithreaded programming
A Parallel Simulated Annealing Algorithm with Low Communication Overhead
IEEE Transactions on Parallel and Distributed Systems
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Trading quality for compile time: ultra-fast placement for FPGAs
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Using MPI (2nd ed.): portable parallel programming with the message-passing interface
Using MPI (2nd ed.): portable parallel programming with the message-passing interface
Parallel algorithms for FPGA placement
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Foundations of Parallel and Distributed Programming
Foundations of Parallel and Distributed Programming
Parallel placement for field-programmable gate arrays
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Parallel Simulated Annealing Algorithms for Cell Placement on Hypercube Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Performance Evaluation of MPI Implementations and MPI-Based Parallel ELLPACK Solvers
MPIDC '96 Proceedings of the Second MPI Developers Conference
Dragon2005: large-scale mixed-size placement tool
Proceedings of the 2005 international symposium on Physical design
Modern Multithreading: Implementing, Testing, and Debugging Multithreaded Java and C++/Pthreads/Win32 Programs
High-quality, deterministic parallel placement for FPGAs on commodity hardware
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Proceedings of the 45th annual Design Automation Conference
Parallel placement for FPGAs revisited
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
MAPS: multi-algorithm parallel circuit simulation
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
An evaluation of parallel simulated annealing strategies with application to standard cell placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FPGA placement by graph isomorphism (abstract only)
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Parallel neighbourhood search on many-core platforms
International Journal of Computational Science and Engineering
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One of the current main challenges of the FPGA design flow is the long processing time of the placement and routing algorithms. In this paper, we propose a hybrid parallelization technique of the simulated annealing-based placement algorithm of VPR developed in the work of Betz and Rose (1997). The proposed technique uses balanced region-based partitioning and multithreading. In the first step of this approach placement subproblems are created by partitioning and then processed concurrently by multiple worker threads that are run on multiple cores of the same processor. Our main goal is to investigate the speedup that can be achieved with this simple approach compared to previous approaches that were based on distributed computing. The new hybrid parallel placement algorithm achieves an average speedup of 25× using four worker threads, while the total wire length and circuit delay after routing are minimally degraded.