UNIX network programming
Spectral k-way ratio-cut partitioning and clustering
Proceedings of the 1993 symposium on Research on integrated systems
Trading quality for compile time: ultra-fast placement for FPGAs
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Parallel algorithms for FPGA placement
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Thread Time: A Multi-Threaded Programming Guide with Cdrom
Thread Time: A Multi-Threaded Programming Guide with Cdrom
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Distributed-memory parallel routing for field-programmable gate arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multiway FPGA partitioning by fully exploiting design hierarchy
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast timing-driven partitioning-based placement for island style FPGAs
Proceedings of the 40th annual Design Automation Conference
High-quality, deterministic parallel placement for FPGAs on commodity hardware
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Improving simulated annealing-based FPGA placement with directed moves
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Speeding up FPGA placement via partitioning and multithreading
International Journal of Reconfigurable Computing
Multilevel optimization for large-scale hierarchical FPGA placement
Journal of Computer Science and Technology
Efficient and Deterministic Parallel Placement for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
StarPlace: A new analytic method for FPGA placement
Integration, the VLSI Journal
A fast discrete placement algorithm for FPGAs
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
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Placement and routing are the most time-consuming processes in automatically synthesizing and configuring circuits for field-programmable gate arrays (FPGAs). In this paper, we use the negotiation-based paradigm to parallelize placement. Our new FPGA placer, NAP (Negotiated Analytical Placement), uses an analytical technique for coarse placement and the negotiation paradigm for detailed placement. We describe the serial algorithm and report results. We also report findings related to parallelizing NAP under a multicast networking and multi-threaded operating system environment; the parallel placer is tolerant to multicast packet loss as well as out-of-order packet delivery. Our parallel placer exhibits little performance degradation while attaining speedups of 2 using 3 processors.