VLSI cell placement techniques
ACM Computing Surveys (CSUR)
Analytical placement: A linear or a quadratic objective function?
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Timing driven placement for large standard cell circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Trading quality for compile time: ultra-fast placement for FPGAs
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Optimal partitioners and end-case placers for standard-cell layout
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Timing-driven placement for FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Multilevel optimization for large-scale circuit placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Parallel placement for field-programmable gate arrays
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Proceedings of the 2004 international symposium on Physical design
Recursive bisection based mixed block placement
Proceedings of the 2004 international symposium on Physical design
Multilevel generalized force-directed method for circuit placement
Proceedings of the 2005 international symposium on Physical design
ISPD 2006 Placement Contest: Benchmark Suite and Results
Proceedings of the 2006 international symposium on Physical design
Architecture and details of a high quality, large-scale analytical placer
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Architecture-aware FPGA placement using metric embedding
Proceedings of the 43rd annual Design Automation Conference
High-quality, deterministic parallel placement for FPGAs on commodity hardware
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Towards scalable placement for FPGAs
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
A Graph-Based I/O Pad Pre-placement Technique for Use with Analytic FPGA Placement Methods
VLSID '10 Proceedings of the 2010 23rd International Conference on VLSI Design
Digital Integrated Circuits
GORDIAN: VLSI placement by quadratic programming and slicing optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Implementation and extensibility of an analytic placer
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient and effective analytical placer for FPGAs
Proceedings of the 50th Annual Design Automation Conference
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To date, the best algorithms for performing placement on Field-Programmable Gate Arrays (FPGAs) are based on Simulated Annealing (SA). Unfortunately, these algorithms are not scalable due to the long convergence time of the latter. With an aim towards developing a scalable FPGA placer we present an analytic placement method based on a near-linear net model, called star+. The star+ model is a variant of the well-known star model and is continuously differentiable - a requirement of analytic methods that rely on the existence of first- and second-order derivatives. Most importantly, with the star+ model incremental changes in cost resulting from block movement can be computed in O(1) time, regardless of the size of the net. This makes it possible to construct time-efficient solution methods based on conjugate gradient and successive over-relaxation for solving the resulting non-linear equation system. When compared to VPR, the current state-of-the-art placer based on SA, our analytic method is able to obtain an 8-9% reduction in critical-path delay while achieving a speedup of nearly 5x when VPR is run in its fast mode.