Congestion reduction during placement with provably good approximation bound
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An efficient quadratic placement based on search space traversing technology
Integration, the VLSI Journal
New theoretical results on quadratic placement
Integration, the VLSI Journal
An MTCMOS technology for low-power physical design
Integration, the VLSI Journal
StarPlace: A new analytic method for FPGA placement
Integration, the VLSI Journal
Towards accelerating irregular EDA applications with GPUs
Integration, the VLSI Journal
Proceedings of the International Conference on Computer-Aided Design
Multiobjective layout optimization of robotic cellular manufacturing systems
Computers and Industrial Engineering
SimPL: an algorithm for placing VLSI circuits
Communications of the ACM
An efficient and effective analytical placer for FPGAs
Proceedings of the 50th Annual Design Automation Conference
| Hi-index | 0.05 |
The authors present a placement method for cell-based layout styles. It is composed of alternating and interacting global optimization and partitioning steps that are followed by an optimization of the area utilization. Methods using the divide-and-conquer paradigm usually lose the global view by generating smaller and smaller subproblems. In contrast, GORDIAN maintains the simultaneous treatment of all cells over all global optimization steps, thereby considering constraints that reflect the current dissection of the circuit. The global optimizations are performed by solving quadratic programming problems that possess unique global minima. Improved partitioning schemes for the stepwise refinement of the placement are introduced. The area utilization is optimized by an exhaustive slicing procedure. The placement method is applied to real-world problems, and excellent results in terms of placement quality and computation time are obtained