Vector models for data-parallel computing
Vector models for data-parallel computing
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Graphical models for machine learning and digital communication
Graphical models for machine learning and digital communication
Asynchronous Iterative Methods for Multiprocessors
Journal of the ACM (JACM)
Using SAT for combinational equivalence checking
Proceedings of the conference on Design, automation and test in Europe
System-on-a-chip verification: methodology and techniques
System-on-a-chip verification: methodology and techniques
Iterative Methods for Sparse Linear Systems
Iterative Methods for Sparse Linear Systems
Proceedings of the conference on Design, automation and test in Europe
SIMULATION OF PACKET COMMUNICATION ARCHITECTURE COMPUTER SYSTEMS
SIMULATION OF PACKET COMMUNICATION ARCHITECTURE COMPUTER SYSTEMS
Proceedings of the 2004 international symposium on Physical design
Survey propagation: An algorithm for satisfiability
Random Structures & Algorithms
Direct Methods for Sparse Linear Systems (Fundamentals of Algorithms 2)
Direct Methods for Sparse Linear Systems (Fundamentals of Algorithms 2)
An accurate sparse matrix based framework for statistical static timing analysis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Sparse matrix computations on manycore GPU's
Proceedings of the 45th annual Design Automation Conference
Parallelizing CAD: a timely research agenda for EDA
Proceedings of the 45th annual Design Automation Conference
Towards acceleration of fault simulation using graphics processing units
Proceedings of the 45th annual Design Automation Conference
Design intent coverage revisited
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multigrid on GPU: tackling power grid analysis on parallel SIMT platforms
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Fast circuit simulation on graphics processing units
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Event-driven gate-level simulation with GP-GPUs
Proceedings of the 46th Annual Design Automation Conference
Implementing sparse matrix-vector multiplication on throughput-oriented processors
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
Layout-dependent STI stress analysis and stress-aware RF/analog circuit design optimization
Proceedings of the 2009 International Conference on Computer-Aided Design
Taming irregular EDA applications on GPUs
Proceedings of the 2009 International Conference on Computer-Aided Design
Accelerating large graph algorithms on the GPU using CUDA
HiPC'07 Proceedings of the 14th international conference on High performance computing
Distributed time, conservative parallel logic simulation on GPUs
Proceedings of the 47th Design Automation Conference
GCS: high-performance gate-level simulation with GP-GPUs
Proceedings of the Conference on Design, Automation and Test in Europe
SCGPSim: a fast SystemC simulator on GPUs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
The university of Florida sparse matrix collection
ACM Transactions on Mathematical Software (TOMS)
Implementing survey propagation on graphics processing units
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
GORDIAN: VLSI placement by quadratic programming and slicing optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Recently graphic processing units (GPUs) are rising as a new vehicle for high-performance, general purpose computing. It is attractive to unleash the power of GPU for Electronic Design Automation (EDA) computations to cut the design turn-around time of VLSI systems. EDA algorithms, however, generally depend on irregular data structures such as sparse matrix and graphs, which pose major challenges for efficient GPU implementations. In this paper, we propose high-performance GPU implementations for a set of important irregular EDA computing patterns including sparse matrix, graph algorithms and message-passing algorithms. In the sparse matrix domain, we solve a core problem, sparse-matrix vector product (SMVP). On a wide range of EDA problem instances, our SMVP implementation outperforms all prior work and achieves a speedup up to 50x over the CPU baseline implementation. The GPU based SMVP procedure is applied to successfully accelerate two core EDA computing engines, timing analysis and linear system solution. In the graph algorithm domain, we developed a SMVP based formulation to efficiently solve the breadth-first search (BFS) problem on GPUs. We also developed efficient solutions for two message-passing algorithms, survey propagation (SP) based SAT solution and a register-transfer level (RTL) simulation. Our results prove that GPUs have a strong potential to accelerate EDA computing through designing GPU-friendly algorithms and/or re-organizing computing structures of sequential algorithms.